基於FPGA之5G NR寬頻低延遲數位預失真系統設計與效能分析

Abstract

隨著第五代行動通訊(5GNR)技術的演進，寬頻訊號傳輸已成為主流，然而功率放大器(PowerAmplifier, PA) 在寬頻操作下所產生的非線性失真與記憶效應(memory effects)，嚴重影響了通訊系統的傳輸品質。傳統的數位預失真(Digital Pre-Distortion, DPD) 技術多採用運算複雜度高的記憶模型以補償動態非線性，但這也帶來了龐大的硬體資源消耗與系統延遲。 針對上述問題，本研究旨在於FPGA平台上設計並實作一套具備極低延遲架構的實時數位預失真系統。核心設計理念為「以低延遲架構換取預失真模型之簡化並提升系統效能」，採用基於查找表(Look-UpTable,LUT)的無記憶模型，並結合「雙相位旋轉」技術簡化最小均方(LMS)演算法，以及優化CORDIC硬體架構，大幅降低了回授迴路的運算延遲。本研究假說為：透過極致的低延遲與快速係數更新，系統應能具備更佳的動態追蹤能力，以補償部分記憶效應，提升預失真系統之效能表現。 實驗結果顯示，在20MHz頻寬的5GNR訊號測試中，本系統展現卓越的線性化效能，鄰近通道洩漏比(ACLR)改善幅度達到近15dB。而在160MHz超寬頻訊號測試下，雖受限於無記憶模型之物理極限，系統仍能維持穩定運作並提供一定程度之線性度改善。此外，透過與模擬高延遲系統的交叉比對，證實了本研究提出之低延遲優化架構，在大幅節省運算時間（約20個時脈週期）的同時，展現出比原始架構更優異的線性化效能與系統穩健性。本研究成果驗證了輕量化低延遲DPD架構在實現高效能、低成本通訊終端上的可行性。

With the evolution of Fifth Generation New Radio (5G NR) technology, wideband signal transmission has become mainstream. However, the nonlinear distortion and memory effects induced by Power Amplifiers (PA) under wideband operation severely degrade the transmission quality of communication systems. Traditional Digital Pre-Distortion (DPD)techniques often employ computationally complex memory models to compensate for dynamic nonlinearity, yet this results in significant hardware resource consumption and system latency. To address the aforementioned issues, this study aims to design and implement a real-time digital pre-distortion system with an ultra-low latency architecture on an FPGA platform. The core design philosophy involves ”trading low-latency architecture for the simplification of the pre-distortion model and the enhancement of system performance.” The system adopts a Look-Up Table (LUT)-based memoryless model, incorporates a ”dual-phase rotation” technique to simplify the Least Mean Squares (LMS) algorithm, and optimizes the CORDIC hardware architecture, thereby significantly reducing the computational latency of the feedback loop. This study hypothesizes that through extreme low latency and rapid coefficient updates, the system can achieve superior dynamic tracking capabilities to compensate for partial memory effects, thus enhancing the overall DPD performance. Experimental results demonstrate that the proposed system exhibits excellent linearization performance in 20 MHz 5G NR signal tests, achieving an Adjacent Channel Leakage Ratio (ACLR) improvement of nearly 15 dB. In 160 MHz ultra-wideband tests, although limited by the physical constraints of the memoryless model, the system maintains stable operation and provides a certain degree of linearity improvement. Furthermore, a comparative analysis with a simulated high-latency system confirms that the proposed low-latency optimized architecture not only significantly reduces computational time (by approximately 20 clock cycles) but also demonstrates superior linearization performance and system robustness compared to the baseline architecture. These results validate the feasibility of a lightweight, low-latency DPD architecture for realizing high performance and low-cost communication terminals.