矽金氧半和矽/矽鍺異質結構場效電晶體之低溫特性與1/f雜訊分析

Abstract

隨著量子計算的快速發展，若僅依賴傳統在室溫操作的控制電路，量子位元與控制電路之間所需的傳輸線數量將大幅增加，使大規模量子系統難以實現，因此，能在低溫下運作的Cryo-CMOS已成為量子位元控制與讀出電路的重要候選技術。然而，電晶體在低溫下的電性與室溫顯著不同，現有模型無法準確預測其行為。此外，低頻雜訊會直接影響Cryo-CMOS電路的穩定性與量子位元的相干時間，因此深入研究低溫下電晶體的電性與雜訊特性對量子系統的可靠運作十分重要。 本論文以矽與矽/矽鍺異質結構電晶體為主要研究對象，分析其300 K至4 K溫度範圍內之電性與雜訊特性。透過量測電流與電容對電壓的關係，萃取臨界電壓、次臨界擺幅、載子遷移率等重要參數，並比較元件在不同溫度下的電性變化。實驗結果顯示，矽電晶體的臨界電壓皆隨溫度降低而上升，而次臨界擺幅則因低溫下能帶尾態的參與，使其在溫度下降至約50 K以下時趨於飽和。另一方面，自行製作的矽電晶體之導通電流與載子遷移率未如預期隨溫度降低而提升，顯示低溫下散射機制由聲子散射轉為庫倫與表面粗糙度散射主導。至於矽/矽鍺異質結構電晶體，因量子井的形成，在低溫下展現四階段傳輸機制，並在臨界電壓與次臨界擺幅有明顯的降低。 在低頻雜訊的部分，本論文量測並分析不同溫度與偏壓條件下的1/f雜訊行為。在矽電晶體中，中低電流區域主要由載子數量變動機制主導，在較高電流區域則轉為載子遷移率變動機制與源/汲極電阻雜訊共同主導。此外，低溫下的雜訊幅度高於室溫，推測為低溫下能帶尾態的參與導致陷阱密度增加。而矽/矽鍺異質結構電晶體在4 K 下的雜訊特性則清楚呈現載子於量子井與表面通道之間的轉換，且載子從量子井穿隧至表面並形成第二條傳輸通道的時候出現雜訊上升的現象。

With the rapid development of quantum computing, the number of interconnecting wires using conventional room-temperature electronics will increase significantly, making large-scale quantum systems difficult to realize. Therefore, Cryo-CMOS circuits has become a promising technology for qubit control and readout. However, the electrical properties of transistors differ significantly between cryogenic temperatures and room temperature, and existing models fail to accurately predict their characteristics at cryogenic temperatures. In addition, low-frequency noise can directly impact the stability of Cryo-CMOS circuits and the coherence time of qubits. Thus, it is essential to investigate the electrical and noise characteristics of cryo-CMOS devices for reliable qubit operations. This work investigates the electrical and noise characteristics of silicon and Si/SiGe heterostructure MOS field-effect transistors (FETs) at temperatures from 300 K to 4 K. Current-voltage and capacitance-voltage characteristics are studied to extract threshold voltages, subthreshold swing, and carrier mobility. The experimental results show that, for silicon MOSFETs, the threshold voltage increases as the temperature decreases, while the subthreshold swing saturates below approximately 50 K due to the influence of band-tail states. On the other hand, the on-current and carrier mobility of the fabricated devices at lab do not increase as expected with a decreasing temperature, indicating that Coulomb scattering and surface-roughness scattering dominate since phonon scattering is suppressed at cryogenic temperatures. For the Si/SiGe heterostructure devices, the presence of a quantum well leads to a four-regime conduction behavior at low temperatures, along with a clear reduction in threshold voltage and subthreshold swing. For low-frequency noise analysis, this work measures and evaluates 1/f noise under different temperatures and bias conditions. In silicon MOSFETs, carrier number fluctuation is the primary noise mechanism in the low-current regime, while carrier mobility fluctuation and source/drain resistance noise become dominant for higher current. Furthermore, the noise magnitude increases at cryogenic temperatures, which is attributed to an increase in effective trap density associated with band tail states. In Si/SiGe heterostructure MOSFETs, the noise characteristics at 4 K clearly reflects the transition of carriers between the quantum well and surface channel, with a sharp increase in noise amplitude when carriers in the quantum well tunnel to the surface and form a second conduction path, where the poor oxide interface enhances noise significantly.