基於雙重上電控制機制之靜態隨機存取記憶體型物理 不可仿製功能電路原生穩定性強化設計

Abstract

本論文提出一種採用雙上電控制技術之靜態隨機存取記憶體型物理不可仿製功能電路架構。 由於其雙穩態特性，靜態隨機存取記憶體型物理不可仿製功能電路本質上較為不穩定。高對稱性單元在上電時更易受雜訊干擾，進而產生不穩定的輸出位元。本論文旨在提升原生穩定性，以降低對糾錯碼的使用。所提出的雙重上電控制技術使單一物理不可仿製功能電路單元在相同挑戰條件下可產生兩組彼此獨立的回應。根據上電模式的不同，單元的上電狀態將僅取決於物理不可仿製功能電路單元中交叉耦合反相器內 PMOS 或 NMOS 之間的臨界電壓不匹配。當其中一組回應出現不穩定時，另一組回應可作為備援，提供單元第二次獲得穩定性的機會。 本研究使用 180 納米 CMOS 製程實現測試晶片。在 1.8V 電源與 30 納秒上升斜率條件下，不可仿製功能電路核心於 Low-first 與 High-first 兩種上電模式中分別消耗 5.39 fJ/bit 與 5.19 fJ/bit。量測結果顯示，採用雙上電後之原生 BER 為 0.16%，較未改良之 2.24% 提升 92.85%。其評估指標包含 44.22% 的隨機性與 49.2% 的唯一性。

This thesis presents a static random-access memory (SRAM) based physically unclonable function (PUF) with a dual power-up control technique. An SRAM PUF is inherently more unstable due to its bistable nature. More symmetric cells can be heavily affected by noise and generate unstable output bits. This thesis aims to enhance the native stability of PUFs to reduce the need for Error-Correcting Code (ECC) usage. The proposed dual power-up control technique enables a single PUF cell to generate two independent sets of responses for a single set of challenges. Depending on the power-up mode, the cell response is only dependent on either the threshold voltage mismatch between the PMOS or NMOS pair of the cross-coupled inverter inside the SRAM cell. One of the response sets can be used as a backup if the other is found to be unstable, giving the cell a second chance at stability. Test chips are fabricated in a 180 nm CMOS process. When given a 1.8 V supply and a 30 ns ramp, the PUF core consumes 5.39 fJ/bit and 5.19 fJ/bit during the Low-first and High-first modes, respectively. The measured native BER with dual power-up is 0.16%, which is a 92.85% improvement from the raw value of 2.24%. The evaluated metrics show uniformity of 44.22% and uniqueness of 49.21%.