Ku/K頻段砷化鎵功率放大器、V頻段低功耗LC壓控振盪器及W頻段高增益低雜訊放大器之研究

Abstract

本論文主要包含三個部分。第一部分是應用於第六代行動通訊系統第三頻段的Ku/K 頻段功率放大器設計與結果，使用0.18微米增強型砷化鎵假型高速場效電晶體(pHEMT)製程。第二部分為應用於60 GHz短距離通訊系統之V 頻段低功耗LC壓控振盪器之設計與結果，使用65奈米金氧半場效電晶體製程。第三部分是應用於天文接收機之W 頻段高增益低雜訊放大器設計與結果，使用65奈米金氧半場效電晶體製程。 第一部分為應用於第六代行動通訊系統第三頻段的Ku/K 頻段功率放大器設計。此電路採用三級單端共源極放大架構，實現高增益及高輸出功率之表現，此外由於三五族化合物製程之電晶體相較於金氧半場效電晶體製程較不穩定，故本設計導入LC高通濾波器與小電阻以提升穩定度。量測結果顯示，小信號增益在 15.7 至 21.4 GHz 之間達 5.7 GHz 的 3-dB 頻寬，峰值增益 25.5 dB；大信號量測結果顯示，最大輸出飽和功率為 28.2 dBm，最大功率附加效率達 33.1%，晶片面積為 2.8 平方毫米。 第二部分為應用於60 GHz 短距離通訊系統之V 頻段低功耗LC壓控振盪器之設計。此電路採用電流重複利用拓樸以達成低功耗操作，並以反向耦合變壓器改善振盪啟動條件並產生差動輸出，減少電源與接地干擾。量測結果顯示，振盪頻率範圍為58.3至62 GHz，對應6.2%的頻率調變範圍；相位雜訊於1 MHz與10 MHz偏移頻率處分別為 -93.87 dBc/Hz與 -111.52 dBc/Hz，核心功耗僅2.12毫瓦，最大輸出功率為 -4.3 dBm。晶片總面積為0.56 平方毫米，核心面積為0.07 平方毫米。 第三部分為應用於天文接收機之W 頻段高增益低雜訊放大器。此電路由三級電流重複利用共源極放大級與一級達靈頓疊接式放大級組合而成，藉由增加少量功耗以換取整體增益提升，同時第一級採用源極衰退技術同時改善增益及雜訊匹配。量測結果顯示，此低雜訊放大器3-dB頻寬為73.6 GHz至93.3 GHz，峰值增益28.5 dB，最小雜訊指數6.1 dB，整體直流功耗29.7毫瓦，晶片面積0.53 平方毫米。

This thesis consists of three parts. The first chapter presents the design and measurement results of a Ku/K-band power amplifier (PA) for the 6G FR3 application, fabricated in a 0.18-μm E-mode GaAs pHEMT process. The second chapter describes the design and measurement results of a V-band low-power LC voltage-controlled oscillator (VCO) for 60-GHz short-range communication applications, fabricated in a 65-nm CMOS process. The third chapter demonstrates the design and measurement results of a high-gain W-band low-noise amplifier (LNA) for astronomical receivers, fabricated in a 65-nm CMOS process. The first part focuses on a Ku/K-band power amplifier (PA) designed for the forward-looking 6G FR3 applications. This PA is designed using three-stage single-ended common-source amplifiers in a 0.18-μm enhancement-mode (E-mode) gallium arsenide (GaAs) pseudomorphic high-electron-mobility-transistor (pHEMT) process. Due to the physical constraints, III–V compound transistors are more unstable in contrast to CMOS. Therefore, this PA utilizes LC high-pass filters and small series resistors to enhance the circuit's stability. The measured small-signal result shows that the PA achieves a 3-dB bandwidth of 5.7 GHz, spanning from 15.7 to 21.4 GHz, and a peak gain of 25.5 dB. In addition, the measured large signal result shows that the PA delivers a saturated output power of 28.2 dBm (Psat) and a maximum power-added efficiency (PAEpeak) of 33.1%. The total chip area is 2.8 mm². The second part presents a low-power V-band voltage-controlled oscillator (VCO) designed for 60-GHz short-range communication applications. This circuit utilizes the current-reused topology to achieve low-power operation. By replacing a single large tank inductor with an inverse-coupled transformer, the proposed VCO not only inherits the good phase noise performance of the current-reused VCO but also achieves differential outputs, mitigates the start-up problem, and alleviates disturbances to the power supply and ground. The measurement results indicate that the proposed VCO achieves an oscillation frequency of 58.3 GHz to 62.0 GHz with a 6.2% frequency tuning range. Moreover, the VCO exhibits a phase noise of -93.87 dBc/Hz at a 1 MHz offset frequency and -111.52 dBc/Hz at a 10 MHz offset frequency, accompanied by a low core power consumption of 2.12 mW, and a maximum output power of -4.3 dBm. The total chip area is 0.56 mm², with a core area of 0.07 mm². The third part demonstrates a W-band high-gain low-noise amplifier (LNA) designed for astronomical receivers. The LNA consists of three current-reused common-source stages and one Darlington-cascode stage in the output stage. The stage combination trades slightly more DC power for large gain enhancement. The inductive source degeneration is utilized in the first stage to enhance gain matching and noise matching simultaneously. The measurement results demonstrate that the proposed LNA achieves a small-signal peak gain of 28.5 dB within a 3-dB frequency range of 73.6 GHz to 93.3 GHz. Additionally, within the 3-dB bandwidth, the minimum noise figure is 6.1 dB with the total DC power consumption of 29.7 mW. The total chip area is 0.53 mm².