應用於核酸適體及CRISPR-Cas12a酶電化學生物感測之讀出與記憶體電路

Abstract

本論文分為三個部分：其一為在一結合 CRISPR-Cas12a 酵素與結構切換適體之電化學生物感測平台中，完成CRISPR-Cas12a 轉切割反應實驗設計與量測；其二則為一雜訊整形逐次逼近型類比數位轉換器；最後則是自訂式記憶體儲存系統。 在第一個部分中，我們設計實驗以探討不同濃度的DNA適體對CRISPR-Cas12a 酵素轉切割活性（trans-cleavage activity）的影響，並量測待測適體的電流訊號以量化切割程度。於0 nM、0.65 nM與6.5 nM三種轉化生長因子（TGF-β1）DNA適體濃度下，觀察到電流訊號分別下降2.5%、11%與27.3%，成功以團隊所設計之系統晶片量測到不同濃度對應轉切割反應程度之變化。 為了解析更多種類的適體產生的微小電流變化，本研究第二部分設計一具備三種模式（SAR、一階積分、二階積分）的雜訊整形逐次逼近型類比數位轉換器，採用CIFF（Cascaded Integrators with Feed-Forward）架構，並加入可調變之積分時間與低功耗、低雜訊之電路設計。於每秒一千萬次取樣（10 MS/s）下，SAR模式可達到60.1 dB的信噪比（SNDR）；在100 kHz頻寬內，一階和二階積分模式分別可達到82 dB和95.9 dB的信噪比，對應功耗分別為53.4 μW、98.3 μW及137.7μW。 最後，為配合系統之控制與資料儲存需求，本論文亦提出一套具備10k-bits容量的自訂式靜態隨機存取記憶體架構，支援資料儲存與讀取功能，並透過量測驗證其操作穩定性。相較於標準編譯式記憶體，得以根據應用需求調整設計，在功耗與面積上進行優化，提升其在無線供電系統晶片中的適用性。 第二部分的類比數位轉換器採用TSMC 28-nm CMOS製程，而記憶體電路則是採用TSMC 180-nm CMOS製程。

This thesis is divided into three sections. The first section describes the experimental design which tests CRISPR-Cas12a trans-cleavage activity through an electrochemical biosensing system that unites structure-switching aptamers. The thesis presents a noise-shaping successive approximation register (SAR) analog-to-digital converter in the second section. The third section introduces a custom static random-access memory (SRAM) storage system. The first section included experimental designs to investigate how varying DNA aptamer concentrations affected the trans-cleavage activity of CRISPR-Cas12a. The reporter aptamer's electrochemical current measurement serves to determine how much cleavage has occurred. The DNA aptamer concentrations of 0 nM, 0.65 nM and 6.5 nM for transforming growth factor-β1 (TGF-β1) produced signal decreases of 2.5%, 11% and 27.3% respectively. The experimental results prove that the custom-designed system-on-a-chip (SoC) platform successfully detects trans-cleavage activity changes at different DNA aptamer concentrations. To resolve the small current variations generated by various types of aptamers, the second section introduces a noise-shaping SAR ADC that supports three operating modes—SAR, first-order integration, and second-order integration. The ADC employs the cascaded integrators with feed-forward (CIFF) architecture and integrates tunable integration time as well as low-power, low-noise circuit design. At a sampling rate of 10 MS/s, the SAR mode achieves a signal-to-noise and distortion ratio (SNDR) of 60.1 dB. Within a 100 kHz bandwidth, the first-order and second-order integration modes achieve SNDR of 82 dB and 95.9 dB, respectively. The corresponding power consumptions for the SAR, first-order, and second-order modes are 53.4 μW, 98.3 μW, and 137.7 μW, respectively. The third section presents a customized 10-kbit static random-access memory (SRAM) which functions as system control memory and data storage. The custom implementation allows specific application-based optimization of power and area which makes it suitable for wirelessly powered system-on-a-chip (SoC) platforms beyond what standard memory-compiler macros offer. The memory array supports standard read and write operations, and measurement tests confirmed its operational stability. While the SRAM was implemented using TSMC 180-nm CMOS technology, the analog-to-digital converter was manufactured using the TSMC 28-nm CMOS process.