適用於低溫的14位元500 MS/s可合成數位類比轉換器和10位元5 GS/s 具切換突波消除技術之數位類比轉換器

Abstract

本論文提出兩顆採用 40-nm CMOS 製程的電流式數位類比轉換器，分別針對室溫與低溫操作進行設計。第一顆為 14位元 500-MS/s 的可合成電流式數位類比轉換器，利用數位自動佈局繞線工具實現，並透過單元電流源群聚、專用偏壓軌及插入式繞線結構來減輕自動繞線造成的時間偏差與寄生耦合，得以大幅縮短佈局時間。此數位類比轉換器在供應電壓1.1 V，功耗12.42 mW下於 300 K 可達到超過 50 dBc 的 SFDR 與低於 −66 dBc 的 IM3，在 4 K 時則達到超過 43 dBc 的 SFDR 與低於 −66 dBc 的 IM3。第二顆為 10位元 5-GS/s 的電流式數位類比轉換器，採用切換突波消除技術，其輔助單元的電流僅使用主電流單元的十六分之一倍以降低額外功耗與面積。此數位類比轉換器功耗 72 mW、核心面積為0.054 mm²，在高頻下可大幅提升線性度：於 2.47 GHz 時 SFDR 分別在 300 K 與 4 K 改善最多 6 dBc 與 4 dBc，在頻率為 2.4685±0.0005 GHz的雙音測試下 IM3 亦分別在 300 K 與 4 K 改善超過 12 dBc 與 8 dBc。結果顯示本研究提出的數位類比轉換器架構具備低溫相容、高速運作、線性度提升與降低設計複雜度的優點。

This thesis presents two current-steering digital-to-analog converters (CS-DACs) fabricated in 40-nm CMOS technology for both room-temperature and cryogenic operation. The first design is a 14-bit 500-MS/s synthesizable CS-DAC implemented using digital place-and-route tools. Layout challenges such as auto-routed timing skews and parasitic coupling are mitigated through clustered unit-cell placement, dedicated bias rails, and plug-in routing structures, enabling a significant reduction in layout time while achieving >50 dBc SFDR and <−66 dBc IM3 at 300 K, and >43 dBc SFDR and <−66 dBc IM3 at 4 K while consuming 12.42 mW from a 1.1 V supply. The second design is a 10-bit 5-GS/s CS-DAC with switching glitch cancellation (SGC) is also presented, where the SGC circuit operates at 1/16 of the main current unit to minimize power and area overhead. Consuming 72 mW with a core area of 0.054 mm², this DAC demonstrates significant high-frequency linearity improvement, enhancing the SFDR by up to 6 dBc at 300 K and 4 dBc at 4 K at 2.47 GHz, and improving IM3 by more than 12 dBc at 300 K and 8 dBc at 4 K for two-tone tests with 2.4685±0.0005GHz. These results validate efficient, cryogenic-compatible, and high-speed DAC architectures that achieve reduced design effort and improved linearity.