請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10116
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭正邦(James B. Kuo) | |
dc.contributor.author | Yu-Heng Cheng | en |
dc.contributor.author | 鄭宇亨 | zh_TW |
dc.date.accessioned | 2021-05-20T21:03:08Z | - |
dc.date.available | 2016-07-25 | |
dc.date.available | 2021-05-20T21:03:08Z | - |
dc.date.copyright | 2011-07-25 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-15 | |
dc.identifier.citation | [1] J. B. Kuo,“Low-Voltage SOI CMOS Devices and Circuits,”Wiley, New York,2001.
[2] Y. Inous, K. Sugahara, S. Kusunoki, M. Nakaya, T. Nishimura, Y. Horiba, Y. Akasaka, H. Nakata, “A Tree-Dimensional Static RAM,” IEEE Electron Device Letters, vol. EDL-7,pp.327,May 1986 [3] A.O. Adan, T. Naka, A. Kagisawa, and H. Shimizu, “SOI as a Mainstream IC Technology,” SOI Conf. Dig., 9-12, 1998. [4] K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics ,” Proc. Of IEEE, 85(4), 558-576(1997). [5] R. Troutman and H. Zappe, “A transient analysis of latchup in bulk CMOS,” IEEE Trans. Electron Devices,vol. ED-30, pp.170 , 1983. [6] J.P. Colinge, “Silicon-on-Insulator Technology : Materials for VLSI,” Kluwer Academic Press ,1991. [7] K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEE Trans.Electron Devices, Vol. 44, No. 2, pp. 324-330, Feb.1997 [8] J. Y. Choi, J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicormeter SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 38, pp. 1384-1391, 1991. [9] J. Y. Choi, R. Sundaresan, J. G. Fossum, “Monitoring Hot-Electron-Induced Degradation of Floating-Body SOI MOSFET’s,” IEEE Electron Device Letters,Vol.11,pp.156,April 1990. [10] J. Pretet, D. Ioannon, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs,” Sol. St. Elec., vol. 46, no. 11, pp. 1699-1707, 2002. [11] J. P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Electron Device Letters,Vol.EDL-9,p.97,Feb. 1988. [12] S.S.Chen and J.B.Kuo, “Analytical Kink Effect Model of PD SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, pp. 447-458, March 1997. [13] S.C.Lin and J.B.Kuo, “Temperature Dependent Kink Effect Model for PD SOI NMOS Devices,” IEEE Trans. Electron Devices, pp. 254-258, Feb. 1999. [14] Y. G. Chen, J. B. Kuo, Z. Yu and R.W. Dutton, “An analytical drain current model for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices,’’ Solid-State Electronics, 1995. [15] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144, Oct. 2005. [16] C. F. Machala III, James R. Parker, “ Geometry and Temperature Extensions to the Gummel-Poon Model ” IEEE, 1992. [17] F. Fiori and V. Pozzolo, “Modified Gummel–Poon BJT model for electromagnetic susceptibility prediction,” Proc. Conf. Electromagn. Adv. Applicat. , pp. 151 - 154 ,1995. [18] H. Klose and A. W. Wieder, “The transient integral charge control relation-A novel formulation of the currents in a bipolar transistor,” IEEE Electron Devices, vol. ED-34, pp. 1090-1099, May 1987. [19] R. J. McDonald, “Generalised partitioned charge based bipolar transistor modeling methodology,” Electronics Letters, vol. 24 , no. 21, 13th Oct. 1988. [20] E. V. Ploeg, C.T. Nguyen, S. S. Wong and J. D. Plummer, “Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 41, pp. 970-977, 1994. [21] S.C. Chin, Y. C. Tseng and J.C.S. Woo, “Parasitic Bipolar Turn-On of PD-SOI MOSFETs in Dynamic Logic Circuits,” IEEE International SOI Conference Proceedings, pp. 144-145, Oct. 1996. [22] D. E. Ward and R. W. Dutton, “A Charge oriented model for MOS transistor capacitances,” IEEE Journal Solid-State Circuits ,vol. 13, no. 5, pp. 703-708, 1978. [23] C. H. Chen, J. B. Kuo, D. Chen, and C. S. Yeh, “Modeling the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect,” IEEE ICSICT, pp. 1946 – 1948, Nov. 2010. [24] Y. Zhang, D. K. Schroder, H. Shin, S. Hong, T. Wetteroth and S.R. Wilson, “Abnormal transconductance and transient effects in partially depleted SOI MOSFETs”, Solid-State Electronics, vol. 43, pp. 51-56, 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10116 | - |
dc.description.abstract | 本論文敘述40奈米部份解離絕緣體上矽N型金氧半元件寄生雙載子電晶體之電容模型CBE/CBC。第一章對絕緣體上矽互補式金氧半元件(PD SOI CMOS)作介紹,並比較部份解離絕緣體上矽金氧半元件(PD SOI MOS)與完全解離絕緣體上矽金氧半元件(FD SOI MOS)。第二章先說明部分解離絕緣體上矽金氧半元件(PD SOI MOS)之電流傳導機制並且考慮浮動基體效應(floating-body effect)。接著利用Gummel-Poon model 解釋部分解離絕緣體上矽N型金氧半元件(PD SOI NMOS)之暫態行為。再利用數學分析方法推導部分解離絕緣體上矽N型金氧半元件(PD SOI NMOS)之寄生雙載子電晶體(parasitic bipolar device)電容模型CBE/CBC,且在直流情況下觀察電容行為。第三章為暫態分析,描述出部分解離絕緣體上矽N型金氧半(PD SOI NMOS)元件之寄生雙載子電晶體(parasitic bipolar device)電容CBE/CBC 之上升暫態行為。第四章為最後總結。 | zh_TW |
dc.description.abstract | This thesis describes the model of the parasitic bipolar device in the 40nm PD SOI NMOS, and observes the charges in the thin film via transient analysis. The SOI CMOS device is described in chapter 1. Chapter 2 illustrates current mechanism considering the floating-body effect. For transient analysis , the Gummel-Poon model for the parasitic bipolar device in the PD SOI MOS device is very important. The CBE/CBC capacitance models are important in the Gummel-Poon model for transient analysis. CBE/CBC capacitance behavior during DC is then described. Then in chapter 3, the CBE/CBC capacitance behavior during turn-on transient of PD SOI NMOS device is described. Chapter 4 is the conclusion. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T21:03:08Z (GMT). No. of bitstreams: 1 ntu-100-R98943110-1.pdf: 3190699 bytes, checksum: 05bfee14ac5fc1b9345935622d500c3f (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 口試委員會審定書 #
致謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv 圖目錄 vi Chapter 1 Introduction 1 1.1 絕緣體上矽金氧半元件 2 1.2 部分解離絕緣體上矽(PD SOI)金氧半元件V.S. 完全解 離絕緣體上矽(FD SOI)金氧半元件 5 1.3 部分解離絕緣體上矽金氧半元件之電流傳導機制 8 1.4 結論 9 Chapter 2 部分解離絕緣體上矽N型金氧半元件之寄生雙載子電晶體模型: CBE/CBC Modeling the parasitic bipolar device in the PD SOI NMOS device: CBE/CBC 10 2.1 飽和區汲極電流模型 11 2.2 元件模擬 15 2.3 Gummel-Poon model 19 2.4 Partitioned Charge method: QBE /QBC 22 2.5 寄生雙載子電晶體電容分析:CBE/CBC 26 2.6 結論 32 Chapter 3 部分解離絕緣體上矽N型金氧半元件之寄生雙載子電晶體模型暫態分析 Transient analysis of the parasitic bipolar device in the PD SOI NMOS device 33 3.1 部分解離絕緣體上矽N型金氧半元件暫態分析 34 3.2 寄生雙載子電晶體模型turn-on暫態分析 39 3.3 寄生雙載子電晶體模型turn-off暫態分析 48 3.4 結論 51 Chapter 4 總結 52 REFERENCE 54 | |
dc.language.iso | zh-TW | |
dc.title | 40奈米部份解離絕緣體上矽N型金氧半元件寄生雙載子電晶體電容模型CBE/CBC | zh_TW |
dc.title | Modeling the CBE/CBC Capacitance of the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 葉正信,陳正雄 | |
dc.subject.keyword | 絕緣體上矽金氧半元件,寄生雙載子電晶體,電容模型, | zh_TW |
dc.subject.keyword | SOI,Parasitic Bipolar Device,Gummel-Poon model, | en |
dc.relation.page | 56 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2011-07-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-100-1.pdf | 3.12 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。