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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 郭正邦 | |
dc.contributor.author | Shang-Wei Fang | en |
dc.contributor.author | 方上維 | zh_TW |
dc.date.accessioned | 2021-05-20T21:03:04Z | - |
dc.date.available | 2016-07-25 | |
dc.date.available | 2021-05-20T21:03:04Z | - |
dc.date.copyright | 2011-07-25 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-15 | |
dc.identifier.citation | [1] Semiconductor Industry Association, “International Technology Roadmap for Semiconductors - 2010 Update”, 2010. http://www.itrs.net
[2] Marshall, A., Natarajan, S., “PD-SOI and FD-SOI: A Comparison of Circuit Performance,” Electronics, Circuits and Systems, 2002. 9th International Conference on Vol 1, P.25 - P.28, Sept. 2002. [3] J.Y. Choi, L.G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol.ED-38, p.1384, June 1991. [4] J.Y. Choi, R.Sundaresan, J.G. Fossum, “Monitoring Hot-electron-Induced Degradation of Floating-Body SOI MOSFET’s,” IEEE Electron Device Letters, Vol.11, p.156, April 1990. [5] J.P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Electron Device Letters, Vol.EDL-9, p.97, Feb. 1988. [6] J. B. Kuo and S. C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits,” Wiley Interscience, New York, USA, 440pages pages, Apr. 2004. [7] J. B. Kuo, K. W. Su, and S. C. Lin, “Compact MOS/Bipolar Charge-Control Models of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation-SOI-Technology (ST)-SPICE,” ESSDERC Dig, 480-483, 1999. [8] James B. Kuo, “SPICE Compact Modeling of PD-SOI CMOS Devices,” HKEDM Dig., 2000. [9] Y. G. Chen, J. B. Kuo, Z. Yu, and R. W. Dutton, “An Analytical Drain Current Model for Short-Channel Fully-Depleted Ultrathin Silicon-On-Insulator NMOS Devices,” Solid-State Electronics Vol. 38, No. 12, pp.2051-2057, 1995. [10] C. H. Chen, J. B. Kuo, D. Chen and C. S. Yeh, “Modeling the Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect,” ICSICT, Shanghai, Nov. 2010. [11] Hu, C. et al.: “BSIM4.5.0 MOSFET model user’s manual.” [12] J.C.J. Paasschensand, W.J. Kloosterman, and R. v.d. Toorn, “Model Derivation of Mextram 504, The Physics Behind the Model” Philips Nat.Lab., Unclassified Report NL-UR 2002/806, 2002. [13] J. S. Su, J. B. Kuo, D. Chen and C. S. Yeh, “Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach,” EUROSOI, Grenoble, France, Jan. 2010. [14] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10115 | - |
dc.description.abstract | 本篇論文討論一個考慮浮動基體效應的部分解離絕緣體上矽金氧半元件,透過雙載子電晶體/金氧半元件模型方法建立SPICE的模型進行模擬。第一章先簡介絕緣體上矽金氧半元件及其元件之特性,並且比較部分解離絕緣體上矽和完全解離絕緣體上矽之間的差異。第二章說明了部分解離絕緣體上矽金氧半元件的電流傳導機制,接著利用了雙載子電晶體/金氧半元件模型方法建立起模型,並藉由量測值及二維元件模擬器件驗證了雙載子電晶體/金氧半元件模型方法在直流下的準確性。第三章利用考慮浮動基體效應的部分解離絕緣體上矽金氧半元件之交流模型討論暫態的分析,寄生雙載子電晶體的電流增益因閘極電壓上升時間較長而增大,並利用二維元件模擬驗證了雙載子電晶體/金氧半元件模型方法在暫態下的準確性。第四章結論和未來展望。 | zh_TW |
dc.description.abstract | The thesis reports modeling the 40nm PD SOI NMOS device considering floating-body effect via Bipolar/MOS SPICE model approach. Chapter 1 gives a brief introduction about SOI CMOS devices and the scaling trends, including the comparison of the difference between the PD SOI and the FD SOI CMOS devices. Chapter 2 describes the current conduction mechanism of the PD SOI MOS and the compact model constructed from Bipolar/MOS SPICE model approach. As verified by experimentally measured data and 2D simulation results, the compact model of the PD SOI NMOS provides an accurate prediction under DC condition. Chapter 3 discusses the ac model of the PD SOI MOS devices considering the floating body effect for transient analysis. From the study, during the turn-on transient, the current gain of the parasitic bipolar transistor becomes larger as the longer rise time of the gate voltage. As verified by 2D simulation results, the compact SOI model gives an accurate prediction of transient behavior. Chapter 4 is conclusion and future work. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T21:03:04Z (GMT). No. of bitstreams: 1 ntu-100-R98943075-1.pdf: 5133197 bytes, checksum: c3b9e93b24fdb500dde54d2ffeaeded8 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv 目錄 v 圖目錄 vii 表目錄 x Chapter 1 導論 1 1.1 部分解離及完全解離絕緣體上矽金氧半元件 7 1.2 部分解離絕緣體上矽金氧半電晶體的浮動基體效應 9 1.3 論文架構 11 Chapter 2 考慮浮動基體效應的部分解離絕緣體上矽N型金氧半SPICE模型:直流分析 12 2.1 部分解離絕緣體上矽金氧半之飽和區電流傳導機制 15 2.2 雙載子電晶體/金氧半元件架構 17 2.3 雙載子電晶體/金氧半元件模型 21 2.4 直流模擬驗證及分析 26 2.4.1 模型驗證 26 2.4.2 寄生雙載子電晶體之分析 32 2.5 結論 36 Chapter 3 利用雙載子/金氧半SPICE模型方法之部分解離絕緣體上矽金氧半交流模型的暫態分析 37 3.1 經驗參數值 37 3.2 不同頻率下之寄生雙載子電晶體及M-1之分析 41 3.3 不同頻率下之寄生雙載子電晶體電壓及電荷之分析 47 3.4 結論 53 Chapter 4 結論及未來展望 54 REFERENCE 55 | |
dc.language.iso | zh-TW | |
dc.title | 利用SPICE雙載子電晶體/金氧半元件模型方法分析考慮浮動基體效應的40奈米部分解離絕緣體上矽N型矽金氧半元件 | zh_TW |
dc.title | The Bipolar/MOS SPICE Model Approach for Analyzing 40nm PD SOI NMOS Device Considering Floating-Body Effect | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 葉正信,陳正雄 | |
dc.subject.keyword | 絕緣體上矽, | zh_TW |
dc.subject.keyword | SOI,SPICE, | en |
dc.relation.page | 56 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2011-07-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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