由Ga2O3誘導之二維電子氣所實現的矽基先進電晶體結構

Abstract

隨著摩爾定律推進，電晶體密度雖持續每 18 個月翻倍，但隨著傳統電晶體持續微縮，物理與製程挑戰逐漸浮現，使其發展難以完全符合摩爾定律的預測。同時矽（Si）等傳統半導體材料的物理特性也逐漸逼近極限，限制了其在多種應用環境下的性能。為突破這些限制，寬能隙半導體（Wide Band Gap, WBG）成為新興焦點，其中氧化鎵（Ga2O3）因擁有高達 4.9 eV 的能隙而備受關注，不僅在功率元件與感測器領域展現潛力，也被視為未來電晶體閘極氧化層的候選材料，雖然其相關應用仍處於探索階段。 在本論文中採用 TCAD Sentaurus 軟體進行模擬分析，深入探討氧化鎵（Ga2O3）材料之極化效應（Polarization Effect）以及其對元件通道內載子濃度的調變效應（Carrier Modulation Effect）。透過模擬結果顯示，Ga2O3 具備強烈的自發極化特性，能夠在閘極氧化層與矽（Si）通道界面產生有效的電場，進而明顯調控元件內部的載子分佈與電性表現。 為進一步驗證模擬分析的結果，本研究亦實際進行了以 Ga2O3 作為閘極極化層的高電子遷移率電晶體（HEMT）製作。透過實驗首次嘗試將厚度降至次奈米級（sub-nanometer）的 Ga2O3 薄膜沉積於矽通道元件的閘極氧化層與矽基板之間，以觀察其實際對通道載子調變的影響。然而，實際製程中發現元件存在短路及通道無法有效關閉的問題，我也有進行系統性的分析原因，並思考改善對策。 綜合以上模擬分析與實驗製作，本研究證明了氧化鎵薄膜確實具有調變矽通道元件電性表現的潛力與應用價值，同時也指出了製程技術需進一步精進的關鍵環節。未來透過進一步的製程優化與材料整合研究，預期能充分發揮 Ga2O3 獨特的極化特性，實現其在矽基高效能元件中的創新應用。

With the progression of Moore’s Law, transistor density has continued to double approximately every 18 months. However, as traditional transistors continue to scale down, physical and process-related challenges have emerged, making it increasingly difficult to sustain the trend predicted by Moore’s Law. At the same time, the physical properties of conventional semiconductor materials such as silicon (Si) have approached their fundamental limits, restricting their performance across various applications. To overcome these limitations, wide bandgap (WBG) semiconductors have become a growing research focus. Among them, gallium oxide (Ga2O3), with its large bandgap of up to 4.9 eV, has attracted significant attention. Ga2O3 shows great potential not only in power devices and sensor applications but is also considered a candidate material for future transistor gate dielectrics, although its applications in this field remain in the exploratory stage. In this thesis, TCAD Sentaurus simulations were performed to investigate the polarization effect of Ga2O3 and its impact on carrier modulation within the device channel. Simulation results indicate that Ga2O3 exhibits strong spontaneous polarization, which can induce a significant electric field at the interface between the gate dielectric and the Si channel, effectively modulating carrier distribution and device electrical characteristics. To experimentally validate the simulation results, Ga2O3-based high-electron-mobility transistors (HEMTs) were fabricated. For the first time, sub-nanometer-thick Ga2O3 films were deposited between the gate oxide and the Si substrate to evaluate their effect on channel carrier modulation. However, fabrication results revealed issues such as device short-circuiting and the inability to achieve proper channel turn-off. A systematic analysis was conducted to identify the root causes, and potential solutions for process improvement were considered. Combining simulation and experimental findings, this study demonstrates the potential and practical value of Ga2O3 thin films in modulating the electrical performance of Si-based devices, while also identifying key fabrication challenges that require further optimization. With continued process refinement and material integration, Ga2O3’s unique polarization properties are expected to be fully harnessed, enabling innovative applications in high-performance Si-based devices.