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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張子璿 | zh_TW |
| dc.contributor.advisor | Tzu-Hsuan Chang | en |
| dc.contributor.author | 陳威合 | zh_TW |
| dc.contributor.author | Wei-He Chen | en |
| dc.date.accessioned | 2025-11-27T16:05:57Z | - |
| dc.date.available | 2025-11-28 | - |
| dc.date.copyright | 2025-11-27 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-11-22 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101059 | - |
| dc.description.abstract | 隨著摩爾定律推進，電晶體密度雖持續每 18 個月翻倍，但隨著傳統電晶體持續微縮，物理與製程挑戰逐漸浮現，使其發展難以完全符合摩爾定律的預測。同時矽（Si）等傳統半導體材料的物理特性也逐漸逼近極限，限制了其在多種應用環境下的性能。為突破這些限制，寬能隙半導體（Wide Band Gap, WBG）成為新興焦點，其中氧化鎵（Ga2O3）因擁有高達 4.9 eV 的能隙而備受關注，不僅在功率元件與感測器領域展現潛力，也被視為未來電晶體閘極氧化層的候選材料，雖然其相關應用仍處於探索階段。
在本論文中採用 TCAD Sentaurus 軟體進行模擬分析，深入探討氧化鎵（Ga2O3）材料之極化效應（Polarization Effect）以及其對元件通道內載子濃度的調變效應（Carrier Modulation Effect）。透過模擬結果顯示，Ga2O3 具備強烈的自發極化特性，能夠在閘極氧化層與矽（Si）通道界面產生有效的電場，進而明顯調控元件內部的載子分佈與電性表現。 為進一步驗證模擬分析的結果，本研究亦實際進行了以 Ga2O3 作為閘極極化層的高電子遷移率電晶體（HEMT）製作。透過實驗首次嘗試將厚度降至次奈米級（sub-nanometer）的 Ga2O3 薄膜沉積於矽通道元件的閘極氧化層與矽基板之間，以觀察其實際對通道載子調變的影響。然而，實際製程中發現元件存在短路及通道無法有效關閉的問題，我也有進行系統性的分析原因，並思考改善對策。 綜合以上模擬分析與實驗製作，本研究證明了氧化鎵薄膜確實具有調變矽通道元件電性表現的潛力與應用價值，同時也指出了製程技術需進一步精進的關鍵環節。未來透過進一步的製程優化與材料整合研究，預期能充分發揮 Ga2O3 獨特的極化特性，實現其在矽基高效能元件中的創新應用。 | zh_TW |
| dc.description.abstract | With the progression of Moore’s Law, transistor density has continued to double approximately every 18 months. However, as traditional transistors continue to scale down, physical and process-related challenges have emerged, making it increasingly difficult to sustain the trend predicted by Moore’s Law. At the same time, the physical properties of conventional semiconductor materials such as silicon (Si) have approached their fundamental limits, restricting their performance across various applications. To overcome these limitations, wide bandgap (WBG) semiconductors have become a growing research focus. Among them, gallium oxide (Ga2O3), with its large bandgap of up to 4.9 eV, has attracted significant attention. Ga2O3 shows great potential not only in power devices and sensor applications but is also considered a candidate material for future transistor gate dielectrics, although its applications in this field remain in the exploratory stage.
In this thesis, TCAD Sentaurus simulations were performed to investigate the polarization effect of Ga2O3 and its impact on carrier modulation within the device channel. Simulation results indicate that Ga2O3 exhibits strong spontaneous polarization, which can induce a significant electric field at the interface between the gate dielectric and the Si channel, effectively modulating carrier distribution and device electrical characteristics. To experimentally validate the simulation results, Ga2O3-based high-electron-mobility transistors (HEMTs) were fabricated. For the first time, sub-nanometer-thick Ga2O3 films were deposited between the gate oxide and the Si substrate to evaluate their effect on channel carrier modulation. However, fabrication results revealed issues such as device short-circuiting and the inability to achieve proper channel turn-off. A systematic analysis was conducted to identify the root causes, and potential solutions for process improvement were considered. Combining simulation and experimental findings, this study demonstrates the potential and practical value of Ga2O3 thin films in modulating the electrical performance of Si-based devices, while also identifying key fabrication challenges that require further optimization. With continued process refinement and material integration, Ga2O3’s unique polarization properties are expected to be fully harnessed, enabling innovative applications in high-performance Si-based devices. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-11-27T16:05:57Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-11-27T16:05:57Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
致謝 ii 摘要 iii Abstract iv 目次 vi 圖次 x 表次 xii Chapter 1 Introduction 1 1.1 Overview of Transistor 1 1.1.1 Scaling Trends and Technology Nodes in Moore’s Law 2 1.1.2 Physical Limitations and Challenges 4 1.1.3 Advances and Emerging Technologies in Transistor Fabrication 5 1.2 Evolution of Transistor Architectures 12 1.2.1 Planar MOSFET 12 1.2.2 FinFET 14 1.2.3 Gate-All-Around FET (GAAFET) 18 1.3 Transition to Ultra-Wide Bandgap Materials 20 1.3.1 Silicon Carbide (SiC) and Gallium Nitride (GaN) 23 1.3.2 Gallium Oxide (Ga2O3) 25 Chapter 2 Overview and Integration of Ga2O3 27 2.1 Overview of Ga2O3 27 2.2 Growth techniques for Ga2O3 30 2.3 Applications of Ga2O3 32 Chapter 3 TCAD Simulations of Ga2O3-Enhanced Devices 36 3.1 Fin Field-Effect Transistor (FinFET): Impact of polarization intensity variations on device characteristics 36 3.1.1 Device Structure and Simulation Setup 36 3.1.2 Analysis of DC Transfer and Output Characteristics 39 3.1.3 Comparison of Key Device Parameters and Performance Metrics 43 3.2 Insulated Gate Bipolar Transistor (IGBT): Impact of Ga2O3 Polarization Layer on IGBT Carrier Modulation 48 3.2.1 Device Structure and Simulation Methodology 48 3.2.2 Analysis of Electrical Characteristics and Breakdown Voltage 51 3.2.3 Parametric Analysis of Polarization Layer Extension into the P- Region 58 Chapter 4 Ga2O3/Si HEMT fabrication process 61 4.1 Mask Layout Design and Considerations 61 4.1.1 Alignment Marker 61 4.1.2 Channel Definition 62 4.1.3 Gate Definition 63 4.1.4 Pad Definition 63 4.2 Detailed Fabrication Processes and Ga2O3 Integration 65 4.2.1 Lithography and S/D define 66 4.2.2 Gate deposition and Etching 69 4.2.3 Implantation and RTA 72 4.2.4 Pad metal deposition and lift off 74 4.3 DC analysis of Ga2O3-based HEMT 76 Chapter 5 Conclusion and Future Works 80 5.1 Conclusion 80 5.2 Future work 82 Reference 84 | - |
| dc.language.iso | en | - |
| dc.subject | 寬能隙半導體 | - |
| dc.subject | 氧化鎵 | - |
| dc.subject | 閘極氧化層 | - |
| dc.subject | 載子調變 | - |
| dc.subject | 次奈米厚 Ga2O3 極化層 | - |
| dc.subject | Wide bandgap semiconductor | - |
| dc.subject | Gallium oxide | - |
| dc.subject | Gate dielectric | - |
| dc.subject | Carrier modulation | - |
| dc.subject | Sub-nanometer Ga2O3 polarization layer | - |
| dc.title | 由Ga2O3誘導之二維電子氣所實現的矽基先進電晶體結構 | zh_TW |
| dc.title | Advanced Transistor Structures Enabled by Ga2O3-Induced Two-Dimensional Electron Gas on Silicon | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 114-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 吳育任;吳肇欣;林致廷 | zh_TW |
| dc.contributor.oralexamcommittee | Yuh-Renn Wu;Chao-Hsin Wu;Chih-Ting Lin | en |
| dc.subject.keyword | 寬能隙半導體,氧化鎵閘極氧化層載子調變次奈米厚 Ga2O3 極化層 | zh_TW |
| dc.subject.keyword | Wide bandgap semiconductor,Gallium oxideGate dielectricCarrier modulationSub-nanometer Ga2O3 polarization layer | en |
| dc.relation.page | 88 | - |
| dc.identifier.doi | 10.6342/NTU202504111 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-11-24 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2030-08-06 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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