應用於多尺度穩態熱分析的域分解分割優化

Abstract

本論文提出一套基於最佳化的矩形分割框架，應用於先進半導體封裝之熱模擬中的區域分解法。在既有 DDM 用於積體電路熱模擬的研究成果及探討分割對收斂性影響的基礎上，本研究結合了對熱通量敏感的 HeatTerm 與源自幾何界限的 MemoryTerm，以雙目標最佳化模型形式建構分割策略。所提出的方法設計上相容於多尺度 Neumann–Neumann 求解器，能在提升收斂效率與記憶體可擴展性之間取得平衡，並透過蒙地卡羅擾動增強數值穩健性。 在均勻與非均勻分布、低功耗 SoC 以及系統級晶圓案例中驗證結果顯示，本方法可在確保溫度精度維持於0.3°C 以內的同時，達成最高 40% 的運算時間縮減與最高 68% 的記憶體節省。更重要的是，優化後的分割策略在傳統等分法失敗的情境下，仍能成功維持收斂。綜合而言，本研究所提出之最佳化導向分割，為從晶片級 SoC 到系統級晶圓的熱分析，建立了一條兼具可擴展性與可靠性的途徑。

This thesis presents an optimization-based rectangular partitioning framework for domain decomposition methods (DDM) in thermal simulations of advanced semiconductor packaging. Building on prior DDM applications to IC thermal analysis and convergence studies highlighting partitioning effects, the framework integrates a flux-sensitive HeatTerm with a geometry-driven MemoryTerm derived from geometric bounds. Designed for compatibility with multiscale Neumann–Neumann solvers, the approach balances convergence efficiency and memory scalability, with Monte Carlo perturbations improving robustness. Validation on uniform and non-uniform domains, a low-power SoC, and a waferscale System-on-Wafer (SoW) confirmed temperature accuracy within 0.3 °C, runtime reductions up to 40%, and memory savings up to 68%. Importantly, optimized partitions consistently achieved convergence where equal partitions failed. These findings establish optimization-guided partitioning as a scalable and reliable pathway for thermal analysis across chip-level to wafer-scale integration platforms.