石墨烯基高熱導複合材料用於三維積體電路封裝之研究

Abstract

三維積體電路 (3DIC)可大幅提升元件密度，突破傳統製程的限制，然而其垂直堆疊架構亦導致嚴重的熱集中問題。本篇研究提出透過結合二維石墨烯與一維奈米碳纖維 (CNFs)，有效地提升封裝材料之熱導率。本研究採用兩階段分散策略，將填料導入環氧樹脂中形成連續的熱傳導網絡，而預混製程 (Pre-mixed process) 能夠有效的分散一維/二維材料避免石墨烯回疊 (Re-stacking)。研究中亦探討溶劑選擇的重要性，選擇適當溶劑可確保填料均勻分散並與環氧樹酯基材具有良好介面結合與分散特性。此外製程的應用不限於石墨烯，研究中實現以電絕緣特性佳的氮化硼 (h-BN)進行製備，進一步拓展製程的適配性，研究針對預混填料/環氧樹脂(Premix/Epoxy) 系統提出多項提升垂直熱導的策略，例如引入不同尺度的材料(零維/一維/二維材料)、提升填料分散性、建構微觀垂直熱導網絡，並透過多種量測方法 (例如Hot Disk、雷射閃光法及 ASTM D5470規範) 進行驗證。 為驗證其實用性，研究於微米級銅柱結構的覆晶封裝晶片 (flip-chip) 封裝中進行測試，掃描式超聲波分析 (Scanning Acoustic Tomography, SAT) 結果顯示，材料可實現幾乎完全填充且空洞生成極少。總結來說，本研究建立了一套可擴展的製程策略並證實能夠有效提升垂直熱導，適用於高性能之封裝材料，應用於下個世代 3DIC 及異質整合平台之需求。

Three-dimensional IC (3DIC) integration pushes device density far beyond conventional limits, but the vertical architecture concentrates heat seriously. This work outlines an integrated approach to boost underfill thermal conductivity by pairing two-dimensional graphene with one-dimensional carbon nanofibers (CNFs). A two-stage dispersion route incorporates these fillers into an epoxy, knitting a continuous heat-spreading network. Careful solvent selection, most effectively N-methyl-2-pyrrolidone (NMP), secures uniform dispersion and strong filler–matrix adhesion, while the same premix protocol proves adaptable to electrically insulating h-BN systems, widening the design palette. In the work, strategies are performed to improve the thermal conductivity of the filler/epoxy system. For instance, introducing materials with different dimensions (zero-, one-, two-dimensional material), improving filler dispersion quality, and constructing the thermal dissipation network. Several axial thermal conductivity measurements (Hot Disk, laser-flash, ASTM D5470) provided thermal conductivity evidence, with the graphene/CNF premix outperforming the other cases. Practical relevance was tested on a flip-chip assembly featuring micron-scale copper pillars. Capillary flow trials and Scanning Acoustic Tomography verified near-complete cavity fill with few voids. Collectively, the results establish a scalable strategy for manufacturing high-performance, thermally conductive underfills compatible with next-generation 3DIC and heterogeneous-integration platforms.