一個具有噪聲整形動態放大器和時域噪聲切片的非同步運作增量型三角積分類比數位轉換器

Abstract

本篇論文提出了一個二階增量型三角積分類比數位轉換器。將傳統運算放大器替換為動態基於比較器之放大器，以實現可調頻率功耗。此外，由於基於比較器之放大器的數位操作特性，非同步事件驅動的時脈成為可能，這不僅加快了轉換速度，還消除了對高頻全域時脈的需求。為了放寬基於比較器之放大器的噪聲要求，提出了一種時域噪聲切片技術，利用增量型三角積分類比數位轉換器輸出的不同權重和基於比較器之放大器的噪聲–斜率關係來調整每個週期的噪聲和功率效率，並優化性能指標。此外，還提出了一種噪聲整形技術，分別應用於第一級放大器以壓制閃爍和熱噪聲，及量化器用來更進一步壓抑量化誤差，以實現更好的噪聲和功耗性能。 本晶片採用台積電40奈米互補式金屬氧化物半導體技術製造，操作於三十二萬取樣頻率，並於有效頻寬十六萬赫茲下得到80.1 dB的訊號雜訊失真比。在1.8伏特的電源供應下總共消耗628微瓦，晶片的核心面積小於0.078平方毫米，Schreier的性能評價(FOMs)達到了164.2 dB。

In this thesis, a second-order incremental sigma-delta modulator (ISDM) ADC is presented. We replace the traditional operational amplifiers with dynamic comparator-based (CB) amplifiers to achieve frequency-scalable power consumption. Moreover, owing to the digital-like operation of CB amplifiers, an asynchronous event-driven clocking becomes feasible, which not only speeds up the conversion but also removes the demand for a high-frequency global clock. To relax the noise requirement of the CB amplifiers, a time-domain noise-slicing (TDNS) technique is proposed, taking advantage of the different weights of ISDM ADC outputs and the noise-slope relationship of the CB amplifier to adjust the noise and the power efficiency of each cycle and optimize the figure of merit (FoM). Additionally, proposed noise-shaping (NS) techniques are applied respectively to the first-stage amplifier to suppress flicker and thermal noise, and to the quantizer to further improve the quantization error, achieving better noise and power performance. Fabricated in TSMC 40nm CMOS technology, the proposed ADC operates at a 350-kHz frequency and achieves 80.1-dB SNDR in a 160-kHz bandwidth. It achieves a Schreier FoM of 164.2 dB and consumes 628 uW under a 1.8 V supply voltage. The active area of this work occupies less than 0.078 mm^2.