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標題: | 具高功率密度功率級之雙路徑降壓轉換器 A Dual Path Buck Converter With A High Power Density Power Stage |
作者: | 楊嘉恩 Chia-En Yang |
指導教授: | 陳中平 Chung-Ping Chen |
關鍵字: | 電源管理積體電路,效率,功率密度, power management integrated circuit,efficiency,power density,PMIC, |
出版年 : | 2024 |
學位: | 碩士 |
摘要: | 首先,本論文在第 1 章中提及目前降壓轉換器在設計上會遇到的困境。與通常用於推動輕負載的低壓差穩壓器相比,功率管理集成電路通常用於推動重負載,這意味著降壓轉換器的效率會因為導通損耗而嚴重降低。
本論文在第 2 章提出了一種全新的雙路徑降壓轉換器的功率級架構。與傳統降壓轉換器的功率級不同,本論文所提出的雙路徑降壓轉換器的功率級不僅可以通過更低的電感電流和更小體積的電感器來消除效率與功率密度之間的耦合,還可以通過預充電功率級的飛電容器,實現更高的電壓降比,從而在相同電壓降比下減少直流電壓轉換器的數量。 本論文會在第 3 章提及全新的雙路徑降壓轉換器的定性和定量分析,而第 4章將專注於模擬,第 5 章則將專注於測量。在這些章節中,全新的雙路徑降壓轉換器將會被拿來與傳統的降壓轉換器進行比較,比照在比較表 5.1 中提到的其他文獻 [1] [2] [3] [4] [5] 。該功率級在使用“0.18 微米 CMOS"製程的情況下,會在固定負載電流為 1 A 時達到 90.3 % 的峰值效率,而在固定轉換比為 0.27 時達到91.3 % 的峰值效率。 本論文將在第 6 章總結所提出的雙路徑降壓轉換器的研究成果,並提供未來的研究方向。 最後,附錄討論了各種類型的降壓轉換器,例如開關電容和開關電感降壓轉換器。還比較了開關電容、開關電感和混合降壓轉換器(雙路徑降壓轉換器)的優缺點。 First of all, the design challenges of buck converters would be mentioned in chapter 1. Especially being compared to an lowdropout regulator is usually adopted in a light load situation, a power management integrated circuit is usually adopted in a heavy load situation, which means the efficiency of a buck converter would be seriously degraded due to conduction power loss. Then, a brand new structure of power stage for a dual path buck converter is proposed in chapter 2. Being compared to the power stage of conventional buck converter, the proposed power stage for a dual path buck converter not only can decouple the tradeoff between efficiency and power density with lower current and smaller volume of inductor, but also achieve a higher voltage stepdown ratio (cost less DCDC converters than the others under the same voltage stepdown ratio) by precharging flying capacitors of power stage. As for analysis, simulation and measurement, both of qualitative and quantitative analysis would be proposed in chapter 3, and simulation would be proposed in chapter 4, and measurement would be proposed in chapter 5. In the chapters mentioned above, the proposed dual path buck converter would be compared to the conventional buck converter, just like the other paper [1] [2] [3] [4] [5] mentioned in comparision table 5.1. The power stage has the peak efficiency 90.3 % at fixed load current equals to 1 A, and peak efficiency 91.3 % at fixed conversion ratio equals to 0.27 under the process ”0.18 um CMOS”. And the research of the proposed buck converter and further research directions would be summarized in chapter 6. Last but not least, many other types of buck converters such as switchedcapacitor and switchedinductor buck converter are mentioned in Appendix. We can tell the pros and cons of switchedcapacitor, switchedinductor, and hybrid buck converter (dual path buck converter, DPBC as well) [6] [7] [8] [9] in this section. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93221 |
DOI: | 10.6342/NTU202401472 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-112-2.pdf 目前未授權公開取用 | 2.87 MB | Adobe PDF |
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