基於FPGA之軟體定義無線電數位預失真系統與插值法效能評估

Abstract

數位預失真技術（Digital Predistortion Technique）旨在改善功率放大器（Power Amplifier）之非線性特性，廣泛的應用於無線通訊系統當中，其概念是透過計算輸出的非線性失真，產生具有反向特性之預失真訊號以抵銷放大器之非線性特性，使輸出盡可能地接近輸入訊號。本論文使用FPGA搭配軟體定義無線電（Software-defined Radio, SDR）射頻（Radio Frequency, RF）模組實現數位預失真系統，並使用PetaLinux建置其作業系統，使其擁有多執行緒之作業能力並享有Linux之軟體生態系，擴張其應用場景。系統採用極座標型式之查找表預失真架構，硬體設計使用高階語言合成技術（High Level Synthesis, HLS）開發，並將線性插值（Linear Interpolation）、二次插值（Quadratic Interpolation）以及三次插值（Cubic Interpolation）演算法實踐於系統中。透過量測證明本論文系統能有效改善失真問題並擴展放大器之線性操作區域。

Digital Predistortion is one of the most wildly adopted techniques in wireless communication systems for improving the linearity of power amplifiers. The fundamental concept involves generating a predistorted signal to compensate the nonlinearity of the PA by calculating its inverse characteristic function. This work implements a DPD system using an FPGA with an SDR RF module, and deploys PetaLinux operating system, enabling it to possess multi-threading capabilities and access to Linux software ecosystem, thereby broadening its potential applications. This system utilized the LUT-based architecture with the polar predistorter and employs High-level synthesis for hardware design. Taking advantage of the development flexibility provided by HLS, this work implements three different interpolation algorithms in the system and compares the differences. Measurement results substantiate the efficacy of this system in mitigating distortion issues and extending the linear region of PA.