利用分子動力學模擬分析銅-銅鍵合中銅和銅以及銅和二氧化矽材料的界面性質

Abstract

晶片的發展一直遵循著莫爾定律 (Moore’s law)，然而隨著集成電路 (Integrated circuits, IC) 尺寸逐漸微縮至其物理極限，必須盡快尋找解決方案，透過垂直堆疊的三維積體電路 (Three-dimensional integrated circuit, 3DIC) 可有效節省空間，而銅-銅鍵合則為其中關鍵技術之一。然而由於尺寸持續微縮，材料界面上的特性、晶格大小、原子排列方向以及分子間的作用力的影響也越來越大，因此本研究利用分子動力學模擬對銅-銅鍵合當中的兩個界面 (銅/銅、銅/二氧化矽) 進行研究。首先，我們先針對銅/二氧化矽界面的結構進行分析，考慮結構不同晶格大小及溫度的差異，分析結構的變化、應力分布及其力學性質，由研究結果我們可以發現：銅原子具有擴散性，因此會在銅和二氧化矽材料之間形成一個同時包含銅及二氧化矽原子之過渡區 (transitional zone)，且擴散係數會隨溫度升高而變大，而原子等級 von-Mises stress 也在過渡區有最大值，結構中原子等級 von-Mises stress 會隨溫度升高而變大，但受晶格大小差異影響不大。接著，我們對銅/銅界面的結構進行分析，考慮上下層銅原子之間間隔不同大小及表面有無孔洞，在不同溫度下分析其結構的變化及應力分布，由研究結果我們發現：銅原子在平坦的表面並不會產生擴散現象，擴散是由孔洞周遭開始的，且越淺的孔洞擴散的越快，此外，擴散係數也會隨溫度升高而變大，而原子等級 von-Mises stress 在三個結構當中差異不大，孔洞周圍也無應力集中現象，但原子等級 hydrostatic stress 和膨脹空間有關，膨脹空間越大，則原子等級 hydrostatic stress 會越小。此研究使我們對於不同溫度下的界面表現有更深入的了解，並希望此研究能協助將來在半導體相關材料的開發和研究。

The semiconductor industry has always followed Moore’s law, but as integrated circuits (ICs) approach their physical size limits, finding solutions becomes crucial. Three-dimensional integrated circuits (3DIC) with vertical stacking offer a space-saving solution, and Cu-Cu bonding plays a crucial role. However, as the ICs continues to shrink, the interfacial effects, grain size, crystal orientation, and interaction between atoms become increasingly significant. This study utilizes the molecular dynamics simulation to investigate the two interfaces (Cu/Cu, Cu/SiO2) in Cu-Cu bonding. Firstly, the analysis focus on the interfacial structures of Cu/SiO2, considering the different grain sizes and temperatures. We examine the structural changes, stress distribution, and mechanical properties of the structures. From the research findings, we observe that Cu atoms exhibit diffusion phenomena, leading to the formation of a transitional zone between the Cu and SiO2 materials, containing both Cu and SiO2 atoms. The diffusion coefficient increases with temperatures. Additionally, the atomic-level von-Mises stress reaches its maximum value in the transitional zone. The atomic-level von-Mises stress increases with temperatures, but is not significantly affected by grain size. Next, we analyze the interfacial structures of Cu/Cu, considering different spacings between the upper and lower Cu and the presence of surface voids. We examine the structural changes and stress distribution at different temperatures. The results indicate that Cu diffusion occurs around voids rather than on flat surfaces. Shallower voids promote faster diffusion. The diffusion coefficient increases with temperatures. The atomic-level von-Mises stress shows minimal differences among the structures and no stress concentration is observed around the voids. However, the atomic-level hydrostatic stress is influenced by the expansion space, with larger expansion space resulting in lower atomic hydrostatic stress. This study enhances our understanding of interface behavior at varying temperatures and aims to contribute to future advancements in semiconductor materials research.