可滿足性基礎的自動測試程式生成

Abstract

處理器在產品生命週期內的可靠性需求隨著應用的發展而增加。在此使用情境下軟體自我測試(Software-Based Self-Test)被認為是一種解決辦法。然而過去大多數的研究在生成測試程式時都牽涉到大量的硬體設計知識，這使得自動化程度降低。在本論文中，我們提出了一種只使用到簡單設計知識的自動測試程式生成器。它的基本概念是用指令序列實現自動測試圖樣生產器(Automatic Test Pattern Generation)所生成的檢測狀態。我們的核心技術是將檢測狀態視為要被滿足的值並尋找能夠使之滿足的主要輸入，藉此推導出能實現檢測狀態的指令序列。為了刪減滿足性問題(satisfiability)的搜尋空間，我們的方法將測試樣板與滿足性解答器結合並提出了一種基於檢測狀態統計來決定滿足順序的方法，它能夠維持測試品質並加速測試程式生成。 此外，針對暫存器堆(Register file)這種常見的模組，我們也提出了一個可根據流水線結構調整的通用測試樣板。它能夠提升測試品質與測試效率。透過所提方法，我們在一個RISC-V處理器上達到90.4%的轉態延故障誤覆蓋率(transition delay fault coverage)。

For processor cores, reliability demand over the product life increase as applications evolve. Software-Based Self-Test (SBST) is considered a solution in this scenario. However, most of the prior SBST techniques involved a lot of hardware design knowledge. In this thesis, we propose an automatic test program generation using trivial design knowledge only. The basic idea is realizing the automatic test pattern generation (ATPG) generated detection state with an instruction sequence. Our key technique treats the detection state as the values-to-be-satisfied and satisfies them by specifying primary inputs (PIs) which are used to derive instruction sequence. To reduce the search space of solving satisfiability (SAT), we combine template and SAT solver and define the priority of values-to-be-satisfied. Based on the statistics of detection states, the definition of priority speeds up the test program generation. For the register file, we propose a generic test template that is adjustable according to the processor’s pipeline architecture. The template helps to improve the test quality and test efficiency. The proposed method is validated on a RISC-V processor and achieves 90.4% transition delay fault coverage.