具有自適應注入鎖定技術之低電壓鎖相迴路

Abstract

中文摘要 隨著製程及物聯網技術的不斷進步，生醫晶片與穿戴式醫療裝置的應用也越來越興起。然而，各項電子產品的生命週期皆受限於電池的壽命長短，因此低功耗的電路設計顯得越來越重要。根據國際半導體科技組織的報告指出，下一世代低功耗電路設計，其供應電壓將下降至0.5V。在人體通訊的積體電路系統中，鎖相迴路負責提供參考頻率。然而，在低電壓環境下，電晶體的電流會變得更加微弱，導致鎖相迴路的操作頻率受到限制。除此之外，在低電壓環境中，雜訊效應也會變得更加明顯，進而使得電路表現變得更差。 本篇論文中將針對上述之議題提出架構上的討論及改善的設計方法。我們提出了一個可以操作在供應電壓0.5伏特的自動注入鎖定之鎖相迴路，其操作頻率為330MHz至730MHz。晶片採用TSMC 90nm標準CMOS製程實現，晶片面積和核心面積分別為0.7621mm2 和 0.1193mm2。當操作頻率為480MHz時並且開啟自動注入的狀態下，位移1MHz的相位雜訊為 -112.3dBc/Hz，積分範圍從1kHz到30MHz的方均根抖動量為4.93ps，參考突波為 -37.27dB，功率消耗為337.2μW。 在供應電壓0.5伏特的條件下，我們將採用改良式之Bootstrapped 技術來提升震盪器的操作頻率。差動對Bootstrapped技術不只可以增加震盪器輸出訊號的震幅，也會增加電晶體驅動電流的能力。同時，使用閘極切換的技術以增加充電汞的操作區域。針對相位雜訊的問題，我們採用了次諧波注入鎖定的技術來抑制震盪器的相位雜訊和抖動。我們的設計同時採用了自動注入鎖定及手動注入鎖定之技術以做為對照。

ABSTRACT Based on the advance of the integrated circuit technologies, applications of biomedical IC and wearable medical devices become more popular. Due to the limitation of electronic power consumption by the batteries, the issues related to low power design for circuits are more important. According to the reports proposed by International Technology Roadmap for Semiconductor (ITRS), supply voltage of general low-power circuits will be scaled down to 0.5V for the next generation applications. In the integrated-circuit system of human body communication (HBC), the phase-locked loop is responsible for providing the reference frequency. However, the current of transistors are much weaker in low voltage environment, which limits the operating frequency of the phase-locked loop. Besides, the noise effect also becomes more severe in low voltage environment, which will lead to a poor performance of PLL output. In this thesis, we proposed an improved solution to the above topics. The proposed circuit is a 0.5V phase-locked loop with adaptive injection-locked technique. The tuning range of the proposed circuit is from 330 to 730MHz. The chip is fabricated in TSMC 90nm Standard CMOS Technology. The chip area and active core area are 0.7621mm2 and 0.1193mm2, respectively. At the output clock of 480MHz, the measured spur level at 30MHz away from the 480MHz clock output is -37.27dB. The measured phase noise at 1MHz offset is -112.3dBc/Hz and the measured rms jitter integrated from 1kHz to 30MHz is 4.93ps with adaptive injection locking. The power consumption of the fabricated circuit is 337.2μW, which is lower than general requirements. The modified bootstrapped technique is adopted to increase the frequency of oscillator under low supply voltage of 0.5V. The swing of oscillator and the driving ability of MOSFET can be increased by using the differential bootstrapped technique. The gate switching is then introduced to the charge pump (CP) in order to increase operation range. The injection technique is adopted to suppress the phase noise and jitter of PLL output clock. Besides, this work is realized with adaptive and manual injection techniques, respectively.