具功率後退功率附加效益提升之功率放大器的實現與應用

Abstract

本論文以TSMC 90 nm CMOS製程實現兩個操作在5.2 GHz的功率放大器。第一個晶片結合了一個發射與接收的開關、一個低雜訊放大器與一個具有雙輸出功率模式的功率放大器，藉由將發射與接收開關納入功率放大器與低雜訊放大器的匹配網路，達到全積體化的共同設計，避免額外的晶片外元件與連接造成額外的損耗與成本，並且透過切換主動元件開起數目及變壓器的電壓與電流關係，可以使得兩種輸出功率模式的最佳組抗點移動到接近同一點。此晶片操作在接收模式的雜訊指數為3.8 dB，操作在傳輸模式時的輸出飽和功率分別為24.9 dBm與17.2 dBm. 第二個晶片透過一個包絡檢測器將輸入訊號轉換為一個相對應的值，並且經過比較電路後，自動調整對應的閘極偏壓，透過此一切換，在功率退後區域可以節省239毫安培的直流電流。

This thesis implements two power amplifiers operating at 5.2 GHz in a TSMC 90 nm CMOS process. The first chip combines a transmit and receive switch (T/R switch), a low noise amplifier and a power amplifier with dual output power modes. By incorporating the T/R switch into the matching network of the power amplifier and the low noise amplifier, a fully integrated co-design is achieved, avoiding additional losses and costs associated with additional off-chip components and connections. And by switching the number of active devices and the voltage-current relationship of the transformer, the optimal impedance of the two output power modes can be moved to near the same point. The chip operates with a noise figure of 3.8 dB in receive mode and an output saturation power of 24.9 dBm and 17.2 dBm when operating in transmit mode. The second chip converts the input signal into a corresponding value through an envelope detector, and after the comparison circuit, automatically adjusts the correspond-ing gate bias, and by this switching, 239 mA quiescent current can be saved in the power back-off region.