晶圓級系統構裝於高速串列通訊介面的訊號完整度設計

Abstract

本論文提出高速串列通訊介面電源與訊號完整度電路模型並探討其電性特性，其中高速串列通訊介面包含操作速率為4Gbps高速並列訊號單端傳輸架構以及操作速率為25Gbps高速串列訊號差動傳輸架構。論文內容主要分為三大部分，一是建立4Gbps高速並列訊號電路模型，在接收端信號眼圖進行分析，提出接收端信號眼圖的增進方法為降低串音干擾以及降低正規化電阻，透過此設計與原本結構相比，成功提升眼圖品質當佈線長度為8mm時最大傳輸頻寬提升35%，並給予佈局設計的橫截面積與最大傳輸頻寬的關係圖，以利根據需求選擇設計佈局。二是在25Gbps高速串列差動訊號部分設計被動式等化器以及FIR等化器補償通道損失，提升訊號完整度性能以及探討等化器使用的極限，透過此設計使眼圖之眼高在操作速率為25Gbps下提升20%，當操作速率提升到50Gbps時眼高提升為43%，以及使用FIR等化器補償25Gbps高速串列差動訊號線微縮後，線寬為0.5μm時提升佈線長度110%，並使用印刷電路板(PCB)尺度放大模型驗證眼圖模擬結果的正確性。三是提出完整的電源供應網路模型，在高速串列通訊介面的電源傳輸阻抗利用模擬軟體萃取參數方法以及選擇擺放去耦合電容能夠抑制電源傳輸阻抗，對於預測及分析未來的訊號/電源完整度共模擬有極大的幫助。

This thesis presents power and signal integrity model for high speed SerDes interface operating at 25 Gbps. High speed SerDes interface includes 4 Gbps high speed single end parallel signal and 25 Gbps differential serial signal. This research is divided into three sections. First, establishing high speed parallel signal circuit model and analyzing the signal eye diagram on the receiving end. Presenting methods to increase receiving end signal eye diagram by decreasing cross talk noise and normalized resistance. Comparing with the original design, successfully increased layout length by 8 mm while increasing 35% the maximum bandwidth. Giving each layout design’s cross sections and maximum bandwidth relational graph for designers to design the most suitable layout. Second, design the high speed differential serial signal with a passive equalizer and FIR equalizer for faster selection to compensate the loss in channel. Thus increasing the integrity of the signal and exploring the limits of the equalizers. Through the eye height design, operating at 25 Gbps increases by 20%, 50 Gbps increases by 43% and using FIR equalizer to compensate 25 Gbps scaling down high speed differential serial signal by line width 0.5 μm increases layout length by 110%. Also, using PCB scaling up model to verify eye diagram simulation results and testing its accuracy. Lastly, presenting the power delivery network model. Aiming at the ground bounce noise of high speed SerDes interface extracting parameter with simulation software, which will be of great help in prediction and analyzing simulations for future signal / power integrity.