精準階層式三維電容粹取之分析與實作

Abstract

由於大型積體電路的快速發展，電路製程的面積不斷的向下發展，隨著不斷縮小尺寸的電路設計，為了得到更精準的模擬結果如靜態時序分析，計算元件之間的電容就變得相當重要。 在這篇論文中，我們分析了階層式電容粹取的演算法和使用精鍊平板的方法來計算電容，並且修改原有的演算法把最小平板的長度限制去除，利用程式自動選取應有的大小。並分析使用階層式電容粹取時的誤差，利用此誤差分析我們可以建立出更好的電位係數矩陣進而計算出電容值。 在第一章中，我們介紹一些有關電容粹取的基本背景。第二章則介紹電容粹取的基本觀念以及相關的演算法。第三章則進入到本論文的重點，首先我們先介紹如何分析階層式電容粹取的演算法，以及使用其演算法後產生的誤差，接著利用此誤差分析，我們分別對自容及互容的部分作深入的探討。在自容部分，我們修改了原有的演算法，利用程式自動選取子平板的大小，以建立出適當的電位係數矩陣。然後再介紹如果在將我們的演算法嵌入至精鍊平板的方法中。第四章則為模擬結果及數據的分析與比較。最後我們在第五章總結這篇論文。

In recent years, the size of chip decreases dramatically due to rapid development of advanced very large scale integration (VLSI) design. With the reduced size of integrated circuit, capacitance extraction has been an important issue while measuring the performance of a circuit. Some simulations like static timing analysis (STA) requires high accuracy of capacitance extraction. Thus how to compute capacitance accurate and fast is necessary for circuit simulation. In this thesis, we analyze and implement hierarchical capacitance extraction. We first analyze the error estimation while applying hierarchical method. Then we introduce how to build a sparse potential coefficient matrix of self-conductor and mutual conductor separately. Then we let our program to select the minimum side length of the smallest panel spontaneously. An algorithm is proposed to control the accuracy and the run time of simulation result by controlling the error factor. We will briefly introduce the background of capacitance extraction in Chapter 1. Chapter 2 presents basic concepts of computing capacitance and related algorithms. We analyze the error factors of hierarchical capacitance extraction and the implementation in Chapter 3. Chapter 4 shows some simulation results of our proposed algorithm and the comparison with other algorithms. Finally, we conclude this thesis in Chapter 5.