3-10 GHz 寬頻平衡式功率放大器

Abstract

本論文以TSMC 0.18μm CMOS製程，搭配兩種被動製程，分別為低溫共燒陶瓷(low temperature co-fired ceramic, LTCC)製程，與玻璃基板積體被動元件(glass substrate integrated passive device, GIPD)製程，並利用覆晶技術結合主被動製程，來實現包含3-10 GHz頻段之寬頻平衡式功率放大器。 我們採用人造左右傳輸線理論來輔助設計功率放大器輸出端之匹配網路，並在輸入端加上阻抗調整網路，進而調整|S21|的平坦度，並使用負回授以增加電路之穩定度。我們並使用寬頻之90o 功率分配器來組合成平衡式放大器，以改善|S11|與|S22|。在平衡式放大器內之單位放大器的量測部分，頻段內之|S21|為12.09±2 dB，PAE在頻段內的最大值為10.2%-14.8%，在OP1dB時之PAE為7.3%-12.4%，OP1dB為12.2-13.2 dBm，飽和功率Psat為14.8-17.0 dBm。

This thesis presents the implementation of 3-10 GHz broadband balanced power amplifiers by combining both active and passive processes. The active process used is TSMC 0.18μm CMOS and the two passive processes used are low temperature co-fired ceramic (LTCC) and glass substrate integrated passive device (GIPD). We use flip-chip interconnects to combine the T18 chips and these two kinds of substrates. We use CRLH transmission line to design the output matching network for power matching, and add the impedance transfromation network at input port to adjust the flatness of |S21|. We also use the technique of negative feedback to ensure the stability. Finally, we use a broadband 90o power splitter to build the balanced amplifier, which improving |S11| and |S22| significantly. The measurement results of the unit amplifier in the balanced amplifier show that at 3-10 GHz, it achieves the gain of 12.09±2 dB, the peak PAE of 10.2%-14.8%, the PAE at OP1dB 7.3%-12.4%, OP1dB of 12.2-13.2 dBm and Psat of 14.8-17.0 dBm.