二百五十億位元每秒之光接收器電路的設計與分析

Abstract

隨著眾多多媒體應用的快速成長，操作於每秒十幾億的高速收發器需要光纖作為傳輸媒介，因為其損耗低於同軸電纜。典型的前端接收器電路包含了一轉阻放大器以及一限幅放大器。轉阻放大器為了達到低的位元錯誤率必須維持低雜訊，而限幅放大器必須提供足夠高的增益和頻寬去將幾毫伏特的電壓放到至幾百毫伏特。 此篇論文主要分為兩個部分。在第二章中，提及使用雜訊抵消的轉阻放大器。裡面將有一個詳細的轉阻放大器之雜訊分析。此晶片由四十奈米互補式金屬氧化物半導體製程製作。此放大器操作於兩百五十億位元每秒且提供68 dBΩ 的整體增益。量測的輸入積分雜訊為3.1μArms。在輸入為兩百五十億位元每秒之2的-7次方-1 的仿真隨機字串序列下，量測得的位元錯誤率小於10的-12次方。此接收器消耗由電源供應器提供的1.2 伏特、93.8 毫瓦。整體面積為0.64 平方公厘。 在第三章中將提及功率可調的限幅放大器，裡面將會有一個限幅放大器參數設計流程。此晶片使用四十奈米互補式金屬氧化物半導體製程製作。此放大器操作於兩百五十億位元每秒且提供64 dBΩ 的整體增益。量測的輸入積分雜訊為2.7μArms。在輸入為兩百五十億位元每秒之2的7次方-1 的仿真隨機字串序列下，量測得的位元錯誤率小於10的-12次方。此接收器消耗由電源供應器提供的1.3 伏特、103 毫瓦。整體面積為1.16 平方公厘。

With the rapid growth of numerous multimedia applications, high-speed transceivers operating at tens of gigabits per second demand the optical fiber to be the media since optical fiber suffers less loss as coaxial cable does [1]. The typical front-end receiver consists of a TIA and a LA. The TIA must introduce low noise to achieve a low BER and the LA must provide an enough gain and bandwidth to amplify the signals from a few of millivolts to several hundreds of millivolts. This thesis is manly divided into two parts. In chapter 2, the noise-canceling transimpedance amplifier is proposed. There is a detailed noise analysis of the TIA. The chip is fabricated in 40nm-CMOS process. Operating at 25 Gb/s, the amplifier provides an overall gain of 68dBΩ. The measured input integrated noise is 3.1μArms and measured BER is < 10^-12 for a 25 Gb/s PRBS of 2^7-1. Its power consumption is 93.8mW/ch from a 1.2V supply. The total area is 0.64mm^2. In chapter 3, the power scalable limiting amplifier is proposed. A design methology of power scalable LA is introduced. The chip is fabricated in 40nm-CMOS process. Operating at 25 Gb/s, the amplifier provides an overall gain of 64dBΩ. The measured input integrated noise is 2.7μArms and measured BER is < 10-12 for a 25 Gb/s PRBS of 2^7-1. Its power consumption is 103mW/ch from a 1.3V supply. The total area is 1.16mm^2.