以原子層沉積技術製備氧化鋅薄膜電晶體之穩定性、電性以及可撓曲性研究

Abstract

氧化物薄膜電晶體極有潛力取代現有矽薄膜電晶體應用於顯示器中。氧化物薄膜電晶體通常需要高溫熱處理來減少製程中生成的缺陷達到好的電性與穩定性。然而，熱處理增加製造的複雜度與成本以及限制可撓曲元件的發展。我們開發一個低溫的原子層沉積整合製程來製備可撓曲氧化鋅薄膜電晶體，此製程藉由連續沉積的介電層、氧化鋅與封裝製程來減少缺陷的生成。此可撓曲氧化鋅薄膜電晶體可達到高載子遷移率(20.2 cm2/Vs)、高穩定性(經過10800秒8伏特閘極偏壓應力情況下，臨界電壓偏移為0.2伏特)以及低次臨界擺幅(0.34 V/dec)，以及經過半徑1.3公分撓曲1400次後沒有任何劣化。 我們避免在介電層、氧化鋅與封裝層沉積製程中本質缺陷的生成以及藉由最佳化封裝層來保護薄膜電晶體受到環境中的影響而造成異質缺陷。我們的關鍵發現為下列所示:(1) 具有高密度氫氧根的介電層表面可以達到完整鍵結的氧化鋅/介電層介面，我們發現氧化鉿表面的氫氧根密度比氧化鋁以及氧化鋯還多，而低溫沉積的介電層表面比高溫沉積的表面多；(2) 在氧化鋅沉積的前幾次循環中，採用沉浸步驟可以允許前驅物與介電層表面的氫氧根充分反應以達到完整鍵結的介面；(3) 高沉積溫度以及延長前驅物清除時間可以獲得高結晶性與低殘留水含量的氧化鋅通道層；(4) 以雙氧水取代水作為氧來源可以有效減少氧化鋅的載子濃度；(5) 低反應性之四異丙醇鈦沉積二氧化鈦封裝薄膜可以避免於封裝製程中增加氧化鋅的載子濃度而劣化元件特性；(6) 加入氧化鋁而形成氧化鈦/氧化鋁複合薄膜，其水氣穿透率可達1×10-6 g/m2-day，可有效消除環境對氧化鋅薄膜電晶體所造成的劣化；(7) 氧化鋅薄膜電晶體的厚度從120奈米減少54奈米可增加其可撓曲性，多虧高品質的介電層、氧化鋅與封裝層即使減少厚度依然保有優異的性質。

Metal-oxide thin film transistors (TFTs) are promising for display applications. However, metal-oxide TFTs usually require high-temperature processing to reduce and remedy defects produced during their manufacturing process, which increased complexity and cost of production and limit their suitability for flexible electronics applications. We developed a low-temperature atomic layer deposition (ALD) process to fabricate flexible ZnO TFTs, where defects in the TFTs were minimized by depositing the dielectric, ZnO channel and passivation layers of the devices in the integrated ALD process. The ZnO TFTs achieved high mobility (20.2 cm2/Vs), good bias-stress stability (0.2 V threshold voltage shift after 8 V bias 10800 s) and low sub-threshold swing (0.34 V/dec), and could be bended to 1.3 cm of radius for 1400 times without any degradation, which was presented for the first time. Our approaches were two-fold: (1) prevent intrinsic defects from forming in the deposition processes of the dielectric, channel, and passivation layers; (2) protect the devices from developing extrinsic defects under the influence of the surroundings by optimizing the passivation layer. Our key findings were as follows: (1) the dielectric surface should have a high concentration of hydroxyl groups to allow it to thoroughly bond with the ZnO channel; for this we found HfO2 to be superior to ZrO2 and Al2O3, and lower deposition temperatures to be superior to higher ones for the dielectric layer; (2) in the first few ALD cycles of the ZnO channel layer, soaking steps should be employed to allow the precursors to fully react with the hydroxyl groups on the dielectric surface, again to ensure complete bonding the interface; (3) the deposition temperature of the ZnO channel should be high, and the purge times of the ALD precursors should be long to obtain high crystallinity and low residual water of the ZnO channel; (4) H2O2 can be used instead of H2O for higher-temperature ZnO processes to reduce oxygen vacancies, which become abundant at higher deposition temperatures with the H2O process; (5) the typically severe passivation-process-induced degradation to ZnO TFTs can be avoided by using a ALD TiO2 passivation process with titanium isopropoxide (TTIP) and H2O as the precursors, where the low reactivity of TTIP prevented it from inducing oxygen vacancy in the ZnO channel as do other ALD precursors; (6) exceptional gas-barrier performance—WVTR ~1×10-6 g/m2-day—can be obtained by combining the TiO2 process with the Al2O3 process to form a TiO2/Al2O3 nano-laminated passivation, which effectively eliminated environment-induced degradations to the ZnO TFTs; (7) the high quality of the ALD dielectric, channel, and passivation layers allowed excellent device functions to be retained even at substantially reduced layer thicknesses (from 120-nm to54-nm), which in turn enabled the devices to obtain high mechanical flexibility.