利用原子層沉積技術成長金氧半電容元件之二氧化鋯閘極介電層於矽基(100)及(110)晶面之研究

Abstract

本論文利用ALD技術以TDMAZ為前驅物沉積高介電係數ZrO2薄膜於(100)及(110)晶面上，得到不同晶面上有不同的ALD成長速率及ALD製程窗口。以ZrO2 為MOS元件介電層在傳統ALD模式有較薄的IL及Dit值，而RPALD模式κ_ZrO2較大，漏電流較小。使用不同沉積模式混合堆疊ZrO2 MOS元件介電層並使用in-situ氮化處理，在(100)晶面上可達到CET=1.29 nm，Jg=1.18×〖10〗^(-4) A/〖cm〗^2，(110)晶面上CET=1.33nm，Jg=9.04×〖10〗^(-4) A/〖cm〗^2。以傳統ALD模式成長Al2O3做為Si與ZrO2間的緩衝層，之後再使用RPALD模式成長ZrO2形成ZrO2/Al2O3 MOS結構並透過退火時間的延長使整體CET降低，漏電流因Al2O3緩衝層幫助在(100)晶面上可達到Jg=1.17×〖10〗^(-4) A/〖cm〗^2，(110)晶面上Jg=4.93×〖10〗^(-5) A/〖cm〗^2。

In this thesis, we used thermal and remote plasma atomic layer deposition (RPALD) technique to deposit ultrathin zirconium oxide (ZrO2) as the high-κ gate dielectric on (100) and (110)-oriented Si substrates. In the first part of this thesis, we reported that the difference in the growth rate of ZrO2 deposition and the electrical characteristics of ZrO2 gate oxide on the (100) and (110)-oriented Si substrates. The difference in the ZrO2 ALD process window of the two ALD modes were demonstrated. The second part of this thesis introduced that the different deposition schemes along with in-situ nitridation, which can provide a significant improvement of capacitance equivalent thickness (CET), leakage current density (Jg), and interfacial state density (Dit). Besides, the Jg was suppressed by the in-situ atomic layer doping of nitrogen. Accordingly, an improved Jg=1.18×〖10〗^(-4) A/〖cm〗^2,D_it=1.55×〖10〗^12 〖cm〗^(-2) 〖eV〗^(-1), and CET=1.29 nm were achieved on Si(100) , on the other hand, Jg=9.04×〖10〗^(-4) A/〖cm〗^2, D_it=3.59×〖10〗^12 〖cm〗^(-2) 〖eV〗^(-1), and CET=1.33 nm were achieved on Si(110). The third part of this thesis investigated the crystalized ZrO2/Al2O3 buffer layer gate stack. A suppressed Jg of 1.17×〖10〗^(-4) A/〖cm〗^2 on Si(100) and 4.93×〖10〗^(-5) A/〖cm〗^2 on Si(110) could be achieved by the insertion of the Al2O3 buffer layer. Finally, we also found that the longer time PMA treatment time could improve the crystallinity of ZrO2 and the κ_eff of the ZrO2 gate dielectric.