一個低電壓啟動且高升壓倍率之獵能電源轉換系統

Abstract

傳統的太陽能模組由太陽能細胞串聯組成。當部分遮蔽效應發生時，太陽能模組的整體輸出效率將會嚴重降低，甚至還可能導致整個太陽能模組損毀。本論文中提出一個電壓轉換系統，能夠直接採用太陽能細胞或其他獵能轉換器提供的0.5V作為輸入電壓。此電壓轉換系統實現於TSMC 0.25μm HV CMOS製程。我們使用電荷泵浦將0.5V電壓提升到2.6V以上，接著在經由切換式電感升壓轉換器提升至11V以提供給電池充電使用。 由於太陽能細胞產生的電壓小於電晶體臨界電壓，無法啟動電荷泵浦的開關電晶體，尤其後級電晶體遭遇基底效應會更為嚴重。有文獻提出使用後級提供自偏壓訊號與雙路架構以解決開關控制電壓小於臨界電壓問題，並使用基極偏壓的方式降低臨界電壓。然而大部分電力電子積體電路所採用的CMOS製程並不提供深N型井技術。在第一顆晶片，我們針對這個電路進行修正，提出全P型輸出開關，去減低基底效應。並使用頻率最佳化控制提高整體效能。量測結果顯示此電路最低能在0.42V的輸入電壓之下將電壓提升至2.6V，且功率級轉換效率(Vout,measured/Vout,ideal)達到80%以上。 在第二顆晶片中，我們採用電流模式升壓轉換器將第一級所產生的電壓提升到11V。佈局後模擬顯示此晶片可以在2.6V到4.2V的輸入電壓之下，穩定的輸出11V電壓。且在10mA到200mA輸出電流之下，轉換效率達82%以上。

The conventional PV module is composed of the series chains of PV cells. When the shading effect happens, the whole output efficiency of the PV array will reduce severely, it will even damage the PV array. In this thesis, a new power conversion system using the 0.5V voltage generated from PV cell or other energy harvesting transducer as input is proposed. This power conversion system is implement with TSMC 0.25μm CMOS HV process. Firstly, we use the charge pumps to convert the voltage to higher than 2.6V respectively. Then, a switching inductor boost converter raise the voltage to 11V for charging the battery. Because the voltage generated by single solar cell is lower than the threshold voltage of transistors, it cannot turn on the switch of charge pump, especially for the transistors at latter stage, which suffer from body effect. Some literatures propose the backward control bias and two-branch structure with body bias to solve the threshold voltage problem. However, most of the CMOS processes which are used in power electronics integrated circuit does not provide the deep n-well technique. In our first chip, we modify these architectures and propose the all P-type output switch technique to reduce the body effect. To enhance the whole efficiency, a switching frequency optimization (SFO) control is adopted. The measurement result shows that this chip can provide 2.6V output voltage with 0.42V input voltage, and the conversion efficiency of power stage (Vout,measured/Vout,ideal) is higher than 80%. In the second chip, we adopt a current mode boost converter to rise the voltage generated by first chip to over 11V. the post-layout simulation result shows that this chip can provide 11V output voltage stably under 2.6~4.2V supply voltage. And the output current can be in the range of 10mA to 200mA with efficiency over 82%.