5G通訊應用之40奈米CMOS混頻器及衛星應用之可調式高鏡像抑制調變器研製

Abstract

此論文分為主要兩大設計類型，其中皆為由互補式金氧半場效電晶體製程實現，第一部份即為利用40奈米設計次諧波降頻混頻器，其中設計頻率為未來5G可行通訊頻段(38 GHz)。第二部分為高鏡像抑制調變器，利用180奈米實現可調式主動分波器之調變器應用於衛星通訊(17.5-21GHz、27.5-31GHz)，現今無線通訊和網絡，更重視於高數據率傳輸及高頻譜效率，使用高階QAM的成本而提高頻譜效率，需要更高的訊雜比（SNR）與錯誤碼率性能，同時由於 Multi-gigabit無線傳輸的需求，許多研究紛紛投入寬頻毫米波(MMW) 的通訊系統，而為了達到更高的資料傳輸量則需要更多的頻寬。若欲達及上述目標，主要必須具備良好的IQ平衡，既而產生有效的鏡像抑制以利提供高訊號品質。 首先，降頻混頻器有多種混頻架構，而此次設計，使用40奈米互補式金氧半場效電晶體(CMOS)製程，採用Source-Driven之混頻架構以輸入本地震盪訊號，另外，在第一級倍頻器之輸出級加上一級放大器以利推動混頻器，而於輸出級再加上電流操縱(Current Steering)之可調增益之放大器(Variable Gain Amplifier)輸出IF訊號。本地訊號功率為9dBm，操作頻率為32GHz至40GHz及本地訊號頻率為18GHz到22GHz，此設計之混頻器提供 2~8 dB 之可調增益，在操作頻率38GHz之下，提供-5.12 dBm (OP1dB)。 另加提出以180奈米互補式金氧半場效電晶體(CMOS)製程，欲設計出寬頻18-50GHz且可調式之高鏡像抑制調變器，以往設計，多以被動電路分配相位及振幅達及高鏡像抑制效果，而在此次設計分為兩個部分，增加可調電容及可調電阻調整振幅及相位之機制，得以在特定頻率皆可維持高鏡像抑制表現，在於輸入損耗及可調線性度之權衡。第一調變器實現於17-25GHz之-6±2 dB轉換損耗、26-50GHz之-17±2 dB轉換損耗，分別於操作頻率21GHz和23GHz，提供-8.16 dBm及-9.03 dBm之輸出功率，於23GHz可達30 dB鏡像抑制。第二調變器實現於17-25GHz之-7±2 dB轉換損耗、26-50GHz之-17±2 dB轉換損耗，可於操作頻率21GHz，提供較高之輸出功率-6.51 dBm，於29GHz可達42dB高鏡像抑制

The thesis presents two design parts. In the first part, the down-conversion mixer is designed in 40-nm CMOS process. The frequency is at 38 GHz which is potential for 5G communication in the future. In the second part, the modulators are designed for satellite communications with active divider in 180-nm CMOS process at downlink frequencies from 17.5 to 21 GHz and uplink frequencies from 27.5 to 31 GHz. Currently, high data rate and high spectral efficiency is the main trend for wireless communication. The cost of using higher order QAM to improve spectral efficiency is that the system requires a higher signal to noise ratio (SNR) to achieve the same BER performance. Meanwhile, the demand of broad bandwidth to deliver multi-gigabit data transmission is significantly increased. There are many research papers reported about multi-gigabit data rates through multi-gigahertz channel. For high date rate, wide bandwidth is also needed. In order to achieve the goal, IQ match is the most important to deliver the high quality of high image rejection ratio (IRR) signal. First of all, there are various types of down-mixers with different driven techniques. In this design, the Source-Driven technique in 40-nm CMOS process is chosen. In addition, a buffer is designed for pushing mixer core behind the output stage of doubler. The variable gain amplifier (VGA) with the structure of current steering is added at the IF port. The proposed down-conversion mixer with IF VGA provides 2~8 dB conversion gain with acceptable tuning linearity from RF frequency of 32-40 GHz and LO frequency of 18-22 GHz. It also provides OP1dB of –5.12 dBm output power at RF frequency of 38GHz and IF frequency of 3.6 GHz under 9 dBm LO pumping power. Two 18-50 GHz IQ modulators with tunable mechanism in 180-nm CMOS process are additionally proposed. To achieve high image rejection ratio (IRR), two different active tuning circuits are proposed in this thesis, which is different from the previous passive only tuning mechanism. The measurement results of modulator1 show the average conversion gain -17±2 dB from 15 GHz to 50 GHz and especially in -7±2 dB from 17 GHz to 25 GHz. The output power of OP1dB is -8.16 dBm at 21 GHz and -9.03 dBm at 23 GHz. The measured image rejection from 15 GHz to 50 GHz is -30 dBc at 23GHz. Especially, Modulator2 provides better performances, measured conversion gain -17±2 dB from 15 GHz to 50 GHz and especially in -7±2 dB from 17 GHz to 25 GHz. The output power of OP1dB is -6.51 dBm at 21 GHz. The measured image rejection from 15 GHz to 50 GHz is -42 dBc at 29 GHz.