無環非同步類延遲非敏感電路之統一建模與高效效能分析

Abstract

由於積體電路製造過程中的變異問題，非同步電路的設計愈來愈受到矚目。 過去非同步電路的效能分析大部分是以全緩衝器(full buffer)為主，半緩衝器(half buffer)的分析仍然缺乏系統性及精確的作法。 在這篇論文中，我們提出了一個針對四相協議(four-phase protocols)非同步電路的統一建模。 我們因此可以獨特地針對不同的類延遲非敏感(quasi-delay insensitive)電路(包含著名的預先充電全緩衝器(pre-charged full buffer)、預先充電半緩衝器(pre-charged half buffer)、弱狀態半緩衝器(weak conditioned half buffer)與零協定邏輯(null convention logic))進行高效效能分析。 我們將以往兩個方法「以線性規劃為主的分析」及「靜態效能分析」可套用的範圍由有限制的全/半緩衝器擴展為所有可能的電路。 藉此我們可以創先直接地比較這兩種方法。 此外，我們更提出了一種改良過的靜態效能分析來增進分析的準確性。 實驗結果顯示靜態效能分析比起線性規劃分析有平均五個數量級的加速，同時線性規劃分析比起靜態效能分析給予7\%到22\%準確的週期時間。 我們的結果能對於提供廣泛的類延遲非敏感電路能延展的效能分析來說是十分重要的。

Asynchronous design methodologies gain recent extensive attention due to the variability issues in fabricating nanometer integrated circuits. Prior work on asynchronous pipeline performance analysis mostly focused on full buffer pipelines. To date half buffer performance analysis still lacks a systematic and precise treatment. In this thesis, we propose a general framework abstracting four-phase asynchronous protocols and thus uniquely enable efficient performance analysis on various acyclic quasi-delay insensitive (QDI) pipelines (including the well-known pre-charged full buffer (PCFB), pre-charged half buffer (PCHB), weak-conditioned half buffer (WCHB), and null convention logic (NCL)) whose analysis has been challenging, if not impossible. Two approaches, linear programming-based performance analysis (LPA) and static performance analysis (SPA), that were applicable only to restricted set of full-buffer and half-buffer pipelines, respectively, are extended to support the entire set of considered pipelines. Thereby the two approaches can be directly compared for the first time. Moreover, an improved SPA is proposed to enhance the accuracy. Experiments show that on average SPA achieve five orders of magnitude speedup over LPA, while LPA may provide 7\% to 22\% tighter cycle time estimation than SPA. Our results are essential to scalable performance analysis for a comprehensive set of QDI circuits.