快速診斷組合邏輯與掃描鏈橋接錯誤之結構化簡技巧

Abstract

本論文提出四種組合型電路與掃描鏈短路型錯誤的模組，這種短路型錯誤的一端是屬於組合型電路，而另一端屬於掃描鏈。根據實驗結果顯示，此種組合型電路與掃描鏈短路型錯誤有別於所有已知的錯誤，而是會受到掃描進入的影響。本論文使用一個鄰近電路配對擷取演算法去利用電路的實體設計布局快速找出可能發生短路的相鄰電路組。本論文提出兩組結構化簡技巧快速去除不可能的電路組以增進程式執行速度。在ISCAS’89基準電路的實驗顯示，平均而言對組合型電路與掃描鏈短路型錯誤的診斷結果準確率為最多四組鄰近電路配對。當錯誤資料相當有限時，本論文提出的技術仍然十分有效。本論文展示了以軟體診斷組合型電路與掃描鏈短路型錯誤的可能性。

This thesis proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that run time is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only ten failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software.