硬體實作取向正規類迴旋低密度奇偶校驗碼之基因搜尋演算法

Abstract

Gallager’s Low-Density Parity-Check (LDPC) codes have recently received a lot of attention because of their excellent performance and low decoding complexity. Since that the hardware complexity is lower than that of Turbo codes, LDPC codes have been widely considered as next-generation error-correcting codes for many real-word applications. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. This thesis presented a genetic algorithm (GA) based regular quasi-cyclic LDPC code search algorithm with hardware and coding gain considerations. Hardware constraint, average girth and bit error rate simulation are used as criterions to select the best code candidates in GA algorithm. An efficient LDPC matrix representation is proposed for the GA algorithm. The results show that our algorithm can efficiently pick hardware implementation friendly LDPC codes with good coding gain performance.