導管式類比數位轉換器的設計與實現

Abstract

摘要 隨著無線通訊系統和個人可攜式電子產品的快速成長，以及CMOS製程技術的快速演進，對低功率、低電壓的積體電路的需求加深。在今日許多電子產品的應用中，使用數位信號處理技術來處理所需的資料，因此也常需要類比信號轉換成數位信號的介面整合在同一系統晶片上，所需的類比數位轉換器必然受到同樣是低功率、低電壓的要求。受益於新MOS製程技術的成長，數位電路設計得到高速、低功率消耗、小面積、低成本的好處，然而對ADC設計而言，降低電源供應、減小元件的本質增益之後，卻加重了實現高增益、高頻寬的放大器的困難度，除此之外，信號的動態範圍減少，也減小了ADC的有效位元數。因此，隨著製程的成長，ADC設計也逐漸遇到瓶頸。 本論文討論基本的導管式類比數位轉換器實現時的限制，針對目前的限制，提出三個解決方法，第一個方法，是傳統以運算放大器為基礎的切換電容電路，提出折疊取樣保持電路的方法，解決乘2放大電路轉換範圍受非線性影響的問題。第二個方法，使用越零偵測為基礎的切換電容電路，提出抵補電壓的補償方法，實現一個8-bit越零偵測型的導管式類比數位轉換器，因為它沒有靜態電流消耗，打破傳統運算放大器設計的限制，使電路更簡化、快速、消耗功率更低。第三個方法[34]，我們發展時域型的類比數位轉換器，把延遲閂鎖迴路應用在類比數位轉換器裡，使這型的轉換器更適合實現在數位的先進製程，這個方法並沒有在這本論文中撰寫。

ABSTRACT Since the explosive growth of wireless communication systems and portable consumer electronics, the low-power low-voltage integrated circuits are indispensable. Many of the applications utilize the digital signal processing to resolve the transmitted information. Therefore, an analog-to-digital converter (ADC) is required between the analog signal and the DSP system. The trend of increasing integration level for integrated circuits has forced the ADC to reside on the same silicon with large DSP and digital circuits. These ADCs operate with the digital circuits in the same voltage which is desirable. Digital circuit design benefits with higher speed, small power, small area, cost-down from state-of-the-art CMOS technologies. For ADC design, the voltage supply and the intrinsic device gain are decreased that are difficult to achieve a high-gain wide-bandwidth amplifier. Besides, the dynamic range of signal is reduced that decreases effective number of bits (ENOB) in ADC circuit. Therefore, The ADC design is becoming a bottleneck in the advance CMOS process. In this paper presents three proposed techniques to resolve these limitations in ADC. First, a pipelined ADC with folded S/H is presented. This method achieves a half swing operation in op-amp based MDAC, and saves about half of pipelined ADC circuits. Second, an op-amp-free MDAC is presented. We propose a zero-crossing based circuit to develop a simple, fast, low power, small area pipelined ADC. This research suits to address scaling issues. These techniques are proposed for ADC designer who can implement an efficient pipelined ADC in advance technology. Finally, we develop time-domain type ADC that more suit for digital CMOS process.