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標題: | 應用於高速有線通訊之數百兆位元決策回授等化器及時脈資料回復電路 Tens-Gb/s Decision-Feedback Equalizers and Clock and Data Recovery Circuits for High-Speed Wire-Line Communications |
作者: | Chang-Lin Hsieh 謝長霖 |
指導教授: | 劉深淵(Shen-Iuan Liu) |
關鍵字: | 時脈資料回復電路,決策回授等化器,接收機, CDR,DFE,Receiver,Linear equalizer, |
出版年 : | 2012 |
學位: | 博士 |
摘要: | 這篇論文主要專注在數百兆位元有線接收器前端的電路設計。論文分為四個部份,第一個部分是一個寬頻的時脈資料回復電路。這個寬頻的時脈資料回復電路使用0.13um製程實現, 此電路能夠運作的頻率範圍為1Gb/s 至16Gb/s。使用所提出的具有雙方向追隨功能的頻率偵測器,在每次執行頻率追隨的功能時都不需要重置壓控振盪器以節省頻率追隨的時間。對於不同的編碼長度的輸入資料,所提出的頻率偵測器均能正常的動作。
在第二個部分,使用65奈米製程實現了一個40Gb/s的決策回授等化器(Decision Feedback Equalizer, DFE)。這個決策等化器使用了提出的背閘回授技巧以達到高操作速度和功耗效率。在第三個部分,使用65奈米製程實現了一個30Gb/s的疊接式決策回授等化器。此疊接式決策回授等化器使用了所提出的合併式加法器/D型正反器。和一級的決策回授等化器比較,此疊接式決策回授等化器能夠在不犧牲操作速度的情形下改善重新定時資料的效能。在第四個部分,一個具有線性等化器和一個半速合併式決策回授等化器/時脈資料回復電路的40Gb/s可調式接收機實現在65奈米製程。所提出的接收機不但能夠減少線性等化器和振盪器的負載,且能夠改善資料及時脈抖動的效能和功率消耗。 This dissertation focuses on the circuit design of the tens-Gb/s receiver front-end. This dissertation consists of four parts, the first part is a wide range clock and data recovery (CDR) circuit. The CDR circuit is implemented in 0.13um CMOS process, and it covers the operation frequency from 1Gb/s to 16Gb/s. By using the proposed bidirectional FD, the frequency acquisition process is automatically accomplished without resetting the VCO to reduce the acquisition time and it works for the various run-length data. In the second part, a 40Gb/s DFE is realized by 65nm CMOS process. The DFE adopts an adder by using the back-gate feedback technique to achieve a high operation speed and power efficiency. In the third part, a 30Gb/s cascaded DFE is fabricated in 65nm CMOS process by the proposed merged adder/DFF structure. This cascade DFE improves the performance of the re-timed data than a one-tap DFE without any speed penalty. In the fourth part, A 40Gb/s adaptive receiver using a linear equalizer and a merged half-rate DFE/CDR circuit is fabricated in a 65nm process. The proposed receiver not only reduces the loadings of the linear equalizer and the VCO, but also improves the jitter performance of the retimed data and recovery clock and power consumption. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/16535 |
全文授權: | 未授權 |
顯示於系所單位: | 電子工程學研究所 |
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ntu-101-1.pdf 目前未授權公開取用 | 8.7 MB | Adobe PDF |
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