一個使用迴路頻寬校正降低製程變異的2.4-3.0十億赫茲次取樣鎖相迴路

Abstract

本論文實現一個使用迴路頻寬校正降低製程變異的2.4-3.0十億赫茲次取樣鎖相迴路，藉由增益控制次取樣相位偵測器與脈衝寬度控制電路，迴路頻寬校正電路可以降低次取樣鎖相迴路對製程的變異，此外，論文中也分析了次取樣鎖相迴路的頻寬與電路參數間的關係，此次取樣鎖相迴路使用台積電40奈米CMOS製程製作且其面積約為0.15 mm2。在供應電壓為1.1 V下，其整體功率消耗為5.81 mW，參考頻率為75 MHz，輸出頻率範圍為2.4-3.0GHz。在輸出頻率為3.0GHz時，量測的方均根抖動量為2.02ps，迴路頻寬校正後，在輸出頻率為3.0GHz，與3.5MHz相比較，五顆晶片的最大迴路頻寬偏差可以從-71.4%減少為-18.5%。

In this thesis, a sub-sampling phase-locked loop (SSPLL) with loop bandwidth is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be relaxed. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75MHz and the output frequency tuning range is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz.