可客製化優化目標之高品質邏輯重繞與再合成技術

Abstract

現代硬體設計日益複雜，加上矽晶圓製造成本的上升，使得對高品質邏輯合成的需求更加迫切。特別是在高階合成所產生的大型電路，以及硬體加速器中重複與再利用元件的普遍存在的情境下，這些都在緊迫的產品上市時程限制下帶來重大的最佳化挑戰。因此，為了滿足多樣化的設計目標，從高效能運算中的需要強力的時序最佳化，到邊緣裝置中的極低功耗需求，如此多樣的設計考量凸顯出能夠依應用特性彈性調整的高品質客製化最佳化技術的需求。 傳統的邏輯合成方法通常以單輸出函數為操作對象，限制了在多輸出電路中共享邏輯的能力，導致最佳化品質不佳。為了克服此限制，本論文提出一套新的電路學習框架 dg，其目標為直接處理多輸出布林函數。該框架建構於 ABC 合成平台之上，結合了函數分解與基於函數頻譜分析的電路複雜度的成本函數，以引導決策樹與決策圖的學習。實驗結果顯示，在 IWLS Contest 基準測試中，相較於 ABC 的基準方法與現有最先進技術，本方法在不增加邏輯層級的情況下，電路可以獲得 21.9% 的面積優化。 除了上述貢獻，本論文進一步提出一種多功能的重繞技術 rewire，該技術能在使用者定義的成本指標下探索功能等價的電路變體。為了解決高強度重繞在可擴展性上的限制，本論文開發了一套並行重合成框架 stochmap，藉由隨機切割與反覆應用於子電路上的重新接線，實現更高的可擴展性。綜合這些方法，在實用電路的各項指標上取得顯著進展，包括電晶體數量減少 21.24%，以及技術映射後面積減少 6.32%。 本論文所提出的方法已於 2025 年 IWLS 程式設計競賽中通過驗證，並獲得第一名，表現優於所有其他參賽者。這些貢獻展現了在邏輯合成領域中，邁向更具彈性、高品質的重要進展。

The increasing complexity of modern hardware designs and the rising cost of silicon fabrication have significantly intensified the demand for high-quality logic synthesis. In particular, the widespread adoption of high-level synthesis for large-scale circuit generation and the prevalence of duplicated and reused components in hardware accelerators introduce substantial optimization challenges under tight time-to-market constraints. To meet these challenges, various design factors must be considered. Design objectives vary widely, from aggressive timing optimization in high-performance computing systems to ultra-low power consumption in edge devices. This diversity underscores the need for high-quality, customized optimization techniques that can be flexibly tailored to meet application-specific requirements. Traditional logic synthesis approaches often operate on single-output functions, which limits their capacity to exploit logic sharing across outputs and results in suboptimal optimization quality for multi-output circuits. To overcome this limitation, this thesis proposes a novel circuit learning framework, dg, that directly targets multi-output Boolean functions. Built upon the ABC synthesis platform, this framework integrates functional decomposition and circuit-complexity-aware cost functions based on spectral analysis to guide decision tree and decision graph learning. Experimental results on IWLS Contest benchmarks demonstrate up to 21.9% improvement in circuit size reduction over both the ABC baselines and the state-of-the-art methods, without incurring logic level degradation. Complementing this contribution, the thesis further introduces a versatile rewiring technique, rewire, which explores functionally equivalent variants of a given circuit under user-defined cost metrics. To address the scalability limitations of high-effort rewiring, a concurrent resynthesis framework, stochmap, is developed to enable scalable deployment through stochastic partitioning and iterative application of rewiring on support-limited subcircuits. Together, these frameworks achieve notable improvements in practical metrics, including a 21.24% reduction in transistor count and a 6.32\% reduction in post-mapping area. The proposed methods were validated in the 2025 IWLS Programming Contest and achieved first place, outperforming all other participants. These contributions mark significant progress toward flexible and high-quality logic synthesis solutions.