基於T型網路耦合宇稱–時序反演對稱之物理不可複製功能

Abstract

本研究利用宇稱–時序反演對稱 (Parity-Time Symmetry, PT Symmetry) 系統在特異點 (Exceptional Point, EP) 附近的高靈敏度特性，透過製程變異所引起的微小物理差異，生成具隨機性與唯一性的裝置識別碼，並將其應用於物理不可複製功能 (Physical Unclonable Function, PUF) 設計。 本論文首先探討宇稱–時序反演對稱電路理論，分析二階與三階之宇稱–時序反演對稱架構，並採用 T 型網路等效模型，取代傳統電感以磁場在空氣中互感耦合，提升穩定性與實作性。在理論與模擬驗證基礎上，以表面黏著元件與印刷電路板實作該架構，並量測 S 參數與暫態響應，結果顯示操作於特異點附近時，系統輸出具有較高變異性，有助於物理不可複製功能實現，亦更進一步執行更嚴謹的 NIST SP 800-22 隨機性測試，結果顯示三階宇稱–時序反演對稱電路操作於特異點附近時有優異的物理不可複製功能表現。 為實現系統小型化，研究亦採用積體被動元件 WIPD 與 U18 CMOS 製程進行晶片化。WIPD 晶片成功縮小電路面積超過 20 萬倍，並保有特異點附近的高靈敏特性，惟受限於製程控制仍偏穩定，導致個體間辨識度有限。而 U18 CMOS 製程則具更高製程精度，卻因誤差過小，反而不利於產生足夠差異以建立有效辨識特徵，顯示高精度的晶片製程在此應用尚存在限制。 本研究證實基於T型網路耦合宇稱–時序反演對稱之物理不可複製功能系統於特異點附近具備高靈敏、可實作、具隨機性與獨特性等優勢，適用於具實體接觸需求或隨身碟存取裝置之安全認證場景。

This study leverages the high sensitivity of parity-time symmetry (PT symmetry) systems near exceptional points (EPs) to generate device identifiers that are random and unique, based on subtle physical discrepancies induced by process variations. And these identifiers are applied to the design of physical unclonable functions (PUFs). The thesis begins by exploring the theory of Parity-Time symmetric circuits, analyzing both second-order and third-order PT-symmetric architectures. A T-network equivalent model is employed to replace traditional inductors with magnetic field-based mutual coupling in air, thereby enhancing both stability and practicality. Based on theoretical analysis and simulation verification, the architecture is implemented using surface-mount components and printed circuit boards. Measurements of S-parameters and transient responses show that when the system operates near an Exceptional Point, its output exhibits greater variability, which facilitates the realization of PUFs. Further, the design is subjected to the rigorous NIST SP 800-22 randomness test suite. Results demonstrate that the third-order PT-symmetric circuit, when operating near an Exceptional Point, delivers excellent PUF performance. To achieve system miniaturization, the study also implements chip-level integration using both the Integrated Passive Device (WIPD) process and the CMOS (U18) process. The WIPD chip successfully reduces the area by over 200k times while reserving the high sensitivity characteristics near the exceptional point. However, the relative stability of the fabrication process constrains the distinguishability among devices. While the U18 process offers even higher precision, its extremely narrow error margin leads to insufficient variation, hindering the development of distinct PUF characteristics. This research confirms that a T-network coupled PT-symmetric system-based PUF operating near exceptional point exhibits advantages such as high sensitivity, practical implementability, randomness, and uniqueness, making it well-suited for secure authentication applications involving physical contact or USB access devices.