請用此 Handle URI 來引用此文件：
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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 鄭宇翔 | zh_TW |
| dc.contributor.advisor | Yu-Hsiang Cheng | en |
| dc.contributor.author | 王裕翔 | zh_TW |
| dc.contributor.author | Yu-Hsiang Wang | en |
| dc.date.accessioned | 2025-08-21T16:23:57Z | - |
| dc.date.available | 2025-08-22 | - |
| dc.date.copyright | 2025-08-21 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-01 | - |
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Rodriguez Larrad, and P. E. Mogensen, “Beyond 5G wireless IRT for Industry 4.0: Design principles and spectrum aspects,” in Proc. IEEE Global Communications Conf. Workshops, 2018. [31] V. Petrov, T. Kurner and I. Hosako, "IEEE 802.15.3d: First Standardization Efforts for Sub-Terahertz Band Communications toward 6G," in IEEE Communications Magazine, vol. 58, no. 11, pp. 28-33, November 2020. [32] M. S. Gupta, "Power gain in feedback amplifiers, a classic revisited," in IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 5, pp. 864-879, May 1992. [33] H. Bameri and O. Momeni, "A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting," in IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 357-370, Feb. 2017. [34] A. Singhakowinta and A. Boothroyd, "Gain capability of two-port amplifiers", Int. J. Electron., vol. 21, no. 6, pp. 549-560, 1966. [35] Z. Wang and P. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99103 | - |
| dc.description.abstract | 本論文講述了太赫茲頻段中低雜訊放大器與次諧波混頻器的設計與實現，並以此分為兩大部分，首先第一部分介紹了一種在D頻段具有極高增益的低雜訊放大器，其由40奈米CMOS製程所實現四級的Gmax-core放大器。傳統上，構建Gmax-core具有無限多種組合方式，通常使用三種線性、無損及互易的元件所組成嵌入網路，然而本論文提出了一種使用變壓器所構成的Y嵌入網路，能夠改良傳統上只能使用單一偏壓的侷限性，將閘極與漏極分開偏壓，這種方法不僅降低了功耗，也實現了更高的增益與更低的雜訊指數。測量結果表示其在143.5 GHz達到峰值增益27.74 dB，3 dB帶寬為7 GHz，雜訊指數約為9 dB。
第二部分設計了兩種300 GHz可上/下變頻的次諧波混頻器，皆為使用65奈米CMOS製程，藉由挑選不同的電路架構，能使電晶體的電阻值產生LO的周期性變化，最後經由並聯電晶體來產生LO的二倍頻再與IF/RF端進行上/下變頻。其模擬結果表明其轉換增益分別為-16.4 dB與-20.4 dB，皆無使用DC pad，不僅大幅縮小晶片面積，並實現了零功耗。 | zh_TW |
| dc.description.abstract | This paper discusses the design and implementation of low-noise amplifiers and sub-harmonic mixers in the sub-terahertz and terahertz frequency bands, dividing the content into two main sections.
Firstly, the initial part introduces a low-noise amplifier with extremely high gain in the D-band, composed of a four-stage Gmax-core amplifier realized in a 40-nm CMOS process. Traditionally, constructing the Gmax-core offers infinitely many combinations, typically achieved using a network composed of three linear, lossless, and reciprocal elements. However, this paper proposes a Y-embedded network constructed with transformers, which improves upon the limitations of traditional single-bias configurations. By biasing the gate and drain separately, this method not only reduces power consumption but also achieves higher gain and lower noise figure. Measurement results demonstrate a peak gain of 27.74 dB at 143.5 GHz, with a 3 dB bandwidth of 7 GHz and a noise figure of approximately 9 dB. In the second part, two sub-harmonic mixers with tunable frequency up to 300 GHz are designed, both utilizing a 65-nm CMOS process. By selecting different circuit architectures, the resistance value of the transistors can be varied periodically to generate LO frequency. Finally, the LO doubling is achieved by parallel transistors, enabling up/down frequency conversion with IF/RF ports. Simulation results show conversion gains of -16.4 dB and -20.4 dB respectively, without using DC pads, leading to significant reduction in chip area and zero power consumption. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-21T16:23:57Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-21T16:23:57Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 ii 摘要 iii Abstract iv 目次 v 圖次 ix 表次 xvi Chapter 1 緒論 1 1.1 研究背景與動機 1 1.2 文獻回顧 2 1.2.1 150 GHz 低雜訊放大器 2 1.2.2 300 GHz混頻器 3 1.3 論文貢獻 6 1.4 章節概要 6 Chapter 2 應用於150 GHz之高增益低雜訊放大器 7 2.1 簡介 7 2.2 Gmax-core 原理與介紹 8 2.2.1 Gma / Gms / U / Gmax 8 2.2.2 Gmax-core滿足條件 10 2.2.3 增益平面 11 2.2.4 Y和Z嵌入網路 13 2.3 電路架構 17 2.4 電路設計與流程 18 2.4.1 偏壓選擇 18 2.4.2 電晶體尺寸選擇 22 2.4.3 電晶體走線影響 25 2.4.4 Gmax-core 設計 26 2.4.5 變壓器設計 28 2.4.6 穩定度 31 2.4.7 Bypass電路 33 2.4.8 電路佈局與Post-sim結果 35 2.5 量測與結果 39 2.5.1 S參數量測 39 2.5.2 OP1dB量測 42 2.5.3 NF量測 43 2.6 問題與討論 46 Chapter 3 300 GHz之次諧波混頻器 47 3.1 簡介 47 3.2 次諧波換頻器原理與介紹 48 3.2.1 疊接式次諧波換頻器 48 3.2.2 並列式次諧波換頻器 49 3.2.3 電路設計規格 51 3.3 串接式開關SHM電路架構 52 3.4 串接式開關SHM電路設計與流程 54 3.4.1 LO馬遜巴倫設計 54 3.4.2 偏壓與電晶體尺寸選擇 57 3.4.3 電晶體走線 61 3.4.4 匹配網路 63 3.4.5 串接式SHM Post-sim結果 66 3.4.6 串接式SHM電路佈局 70 3.5 串接式開關SHM量測與結果 71 3.5.1 串接式下變頻之轉換增益模擬與量測 71 3.5.2 串接式上變頻之轉換增益模擬與量測 76 3.6 並接式開關SHM電路架構 81 3.7 並接式開關SHM電路設計與流程 82 3.7.1 並接式電路設計 82 3.7.2 並接式SHM Post-sim結果 84 3.7.3 並接式SHM電路佈局 87 3.8 並接式開關SHM量測與結果 88 3.8.1 並接式下變頻之轉換增益模擬與量測 89 3.8.2 並接式上變頻之轉換增益模擬與量測 92 3.9 問題與討論 95 Chapter 4 結論 97 REFERENCE 98 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 亞太赫茲 | zh_TW |
| dc.subject | 次諧波混頻器 | zh_TW |
| dc.subject | Gmax-core | zh_TW |
| dc.subject | 太赫茲 | zh_TW |
| dc.subject | 變壓器 | zh_TW |
| dc.subject | CMOS | zh_TW |
| dc.subject | 低雜訊放大器 | zh_TW |
| dc.subject | Gmax-core | en |
| dc.subject | Terahertz | en |
| dc.subject | Sub-harmonic mixer | en |
| dc.subject | Low-noise amplifier | en |
| dc.subject | Transformers | en |
| dc.subject | CMOS | en |
| dc.subject | Sub-terahertz | en |
| dc.title | 150 GHz低雜訊放大器與300 GHz次諧波混頻器之設計 | zh_TW |
| dc.title | Design of a 150 GHz Low-Noise Amplifier and 300 GHz Sub-Harmonic Mixers | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 蔡政翰;林坤佑 | zh_TW |
| dc.contributor.oralexamcommittee | Jeng-Han Tsai;Kun-You Lin | en |
| dc.subject.keyword | 太赫茲,亞太赫茲,CMOS,變壓器,低雜訊放大器,次諧波混頻器,Gmax-core, | zh_TW |
| dc.subject.keyword | Terahertz,Sub-terahertz,CMOS,Transformers,Low-noise amplifier,Sub-harmonic mixer,Gmax-core, | en |
| dc.relation.page | 104 | - |
| dc.identifier.doi | 10.6342/NTU202503352 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2025-08-05 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電信工程學研究所 | - |
| dc.date.embargo-lift | 2025-08-22 | - |
| 顯示於系所單位： | 電信工程學研究所 | |
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| ntu-113-2.pdf | 7.53 MB | Adobe PDF | 檢視/開啟 |
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