利用多級雜訊整形及雜訊耦合技巧之離散時間三角積分調變器設計

Abstract

在現代物聯網(IoT)系統的應用中，高精度的類比數位轉換器(ADC)對於訊號的處理至關重要，影響著整體系統的性能表現。本篇論文將提出兩種不同架構的類比數位轉換器設計，以滿足物聯網設備對於高效能與低功耗的需求。 晶片一為一離散時間之三角積分調變器，以多級雜訊整形(Multi Stage Noise Shaping)來實現高階雜訊整形(Noise Shaping)，並以偽偽差動架構(Pseudo-Pseudo-Differential)來解決單端系統的非線性問題，再採用一個六位元的逐次逼近之類比數位轉換器(SAR ADC)和比較器用來組成另一個多級雜訊整形架構，此架構有助於解決多位元數位類比轉換器(DAC)的非線性問題，同時提升有效位元(ENOB)。此電路在TSMC 180nm製程實現，晶片核心面積為0.466平方毫米，功耗為191.7微瓦，在1 kHz的頻寬下實現了14.13位元的解析度，並達到了92.04 dB的動態範圍。 晶片二同樣採用離散時間三角積分調變器的架構，核心設計為一個二階調變器，並結合一階雜訊耦合(Noise Coupling)整形技術，以實現三階雜訊整形。為了降低系統的功耗與面積，電路運用了運算放大器共享(OTA Sharing)技術，此外，量化器採用四位元的逐次逼近類比數位轉換器，以減少量化雜訊所帶來的干擾，同時以一增量加權平均演算法(Incremental Data Weight Average)來補償多位元數位類比轉換器因不匹配所產生的非線性諧波。此電路同樣在TSMC 180nm製程實現，晶片核心面積為0.273平方毫米，功耗為110.3微瓦，在16 kHz的頻寬下實現了14.5位元的解析度，並達到了170.7 dB的性能指標。

In modern Internet of Things (IoT) applications, a high-precision analog-to-digital converter (ADC) plays a crucial role in signal processing, directly impacting the overall system performance. This thesis proposes two different ADC architectures to meet the high-performance and low-power requirements of IoT devices. Chip 1 is a discrete-time delta-sigma modulator (DTDSM) that employs a 2-1 multi-stage noise shaping to achieve high-order noise shaping. A six-bit successive approximation register (SAR) ADC and a comparator are used to form another multi-stage noise shaping structure, which helps to address the nonlinearity issues in multi-bit DAC and improve the resolution. Additionally, a pseudo-pseudo-differential architecture is adopted to mitigate nonlinearity issues in a single-ended system. This circuit is implemented in the TSMC 180nm process, with a core area of 0.466 mm² and a power consumption of 191.7 µW. It achieves a resolution of 14.13 bits within a 1 kHz bandwidth, a dynamic range of 92.04 dB. Chip 2 also adopts a DTDSM architecture, featuring a 2nd-order modulator combined with 1st-order noise coupling to achieve 3rd-order noise shaping. To reduce power consumption and chip area, the circuit employs the OTA sharing technique. Furthermore, a four-bit SAR ADC is used as the quantizer to minimize interference caused by quantization noise. An incremental data weight average algorithm is implemented to compensate for harmonic distortion caused by the mismatch in multi-bit DACs. It is also fabricated in the TSMC 180nm process, with a core area of 0.273 mm² and a power consumption of 110.3 µW. It achieves a resolution of 14.5 bits within a 16 kHz bandwidth, and a FoMSNDR of 170.7 dB.