極性控制之二維單層二硒化鎢電晶體整合的低功耗與高電壓增益金屬氧化物半導體反相器

Abstract

本研究提出低功耗、高增益的互補式金屬氧化物半導體 (CMOS) 反相器之設計與製作方法，該元件以單層二硒化鎢 (WSe2) 為主體，並利用其內在的雙極性導電行為與可調控極性特性，設計出一組同質性的二維 CMOS 邏輯單元。透過使用三氧化鉬 (MoOx) 作為電洞摻雜層，以及鉍/金 (Bi/Au) 金屬作為 n 型電晶體的低功函數接觸電極，並將 n 型與 p 型元件整合於共同的 HfOx 高介電常數基板上，實現了不需異質材料的極性控制。進一步地，本研究引入 BiOx 作為電子摻雜介面層，以精確調控 n 型元件的臨界電壓 (VT)，從而縮小 n 型與 p 型電晶體之間的 VT 差異，提升反相器的開關對稱性。 在 8 nm 厚的 HfOx 介電層與 VDD = 2 V 的條件下，所製作之 CMOS 反相器展現出完整的邏輯反轉行為，其最大電壓增益可達約 15.5，總雜訊容忍度約為 0.84 VDD，具備極低的靜態功耗優勢。當將介電層厚度縮減至 4 nm 時，由於電場控制能力增強，元件的增益進一步提升至 88.6，總雜訊容忍度則提升至約 0.94 VDD，驗證了在降低等效氧化層厚度的同時可顯著強化切換控制效果。 在引入 BiOx 摻雜層後，反相器之轉移曲線達成理想的開關點 (VM/VDD = 0.5)，增益提升至約 19，雜訊容忍度亦擴展至約 0.895 VDD，顯示出優異的導通對稱性、切換陡度與抗干擾能力。 本研究結果驗證接觸工程方法與 BiOx/MoOx 雙摻雜策略在單一單層材料中實現性能均衡之互補邏輯的有效性。除電性表現外，本研究所建立的製程方法 —— 包括單層 WSe2 的 CVD 成長、圖案化舉離實現選擇性摻雜、以及可擴展 HfOx 基板上的整合 —— 皆具備良好的大面積製程相容性。 整體而言，本研究展現了透過極性控制實現同質 WSe2 CMOS 邏輯的可行性與可擴展性，並作為邁向全二維半導體基礎電子系統之關鍵一步，對於實現高能效、電路等級優異的次世代電子裝置具有重要意義。

This study presents the design and fabrication of a low-power, high-gain complementary metal-oxide-semiconductor (CMOS) inverter based on monolayer tungsten diselenide (WSe2). Leveraging the intrinsic ambipolar transport characteristics and polarity-tunable properties of WSe2, a homogeneous two-dimensional CMOS logic unit was successfully developed. By employing molybdenum trioxide (MoOx) as a hole-doping layer and a Bi/Au metal as a low-work-function contact for the n-type transistor, the n-type and p-type devices were integrated on a common HfOx high-κ dielectric substrate, enabling effective polarity control without the need for heterogeneous materials. To further optimize device performance, a BiOx electron-doping interfacial layer was introduced to finely adjust the threshold voltage (VT) of the n-type device, thereby reducing the VT mismatch between the n- and p-type transistors and improving the inverter's switching symmetry. Under the condition of an 8 nm HfOx dielectric and a supply voltage (VDD) of 2 V, the fabricated CMOS inverter exhibited full logic inversion behavior with a maximum voltage gain of approximately 15.5 and a total noise margin of about 0.84 VDD, while maintaining an extremely low static power consumption. When the dielectric thickness was reduced to 4 nm, enhanced electrostatic control led to a significant increase in gain to 88.6 and a noise margin of around 0.94 VDD, demonstrating the advantages of scaling the equivalent oxide thickness. Upon the introduction of the BiOx doping layer, the inverter’s transfer curve achieved an ideal switching point (VM/VDD = 0.5), with the gain further improved to approximately 19 and the noise margin extended to around 0.895 VDD, indicating excellent symmetry, sharp switching, and strong noise immunity. The results of this study validate the effectiveness of the contact engineering approach and the BiOx/MoOx dual-doping strategy in realizing balanced complementary logic within a single monolayer material. Beyond the favorable electrical performance, the established fabrication process—including CVD growth of monolayer WSe2, patterned lift-off doping, and integration on scalable HfOx substrates—offers excellent compatibility with large-area processing. In summary, this work demonstrates the feasibility and scalability of polarity-controlled homogeneous WSe2 CMOS logic and represents a key step toward the development of fully two-dimensional semiconductor-based electronic systems. The findings hold significant potential for enabling next-generation electronic devices with high energy efficiency and robust circuit-level performance.