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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 資訊網路與多媒體研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98625
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dc.contributor.advisor廖世偉zh_TW
dc.contributor.advisorShih-Wei Liaoen
dc.contributor.author張盛翔zh_TW
dc.contributor.authorSheng-Hsiang Changen
dc.date.accessioned2025-08-18T01:07:38Z-
dc.date.available2025-08-18-
dc.date.copyright2025-08-15-
dc.date.issued2025-
dc.date.submitted2025-08-07-
dc.identifier.citation[1] C. Bai, Q. Sun, J. Zhai, Y. Ma, B. Yu, and M. D. F. Wong. Boom-explorer: RISC-V BOOM microarchitecture design space exploration framework. 2021 IEEE 39th International Conference on Computer Design (ICCD), pp. 292–299. IEEE, 2021.
[2] F. Bellard. QEMU, a fast and portable dynamic translator. 2005 USENIX Annual Technical Conference (USENIX ATC 05), Anaheim, CA, Apr 2005. USENIX Association.
[3] M. Fleischer. Simulated annealing: past, present, and future. Winter Simulation Conference Proceedings, 1995, pp. 155–161, 2025.
[4] G. Hamerly, E. Perelman, J. Lau, and B. Calder. SimPoint 3.0: Faster and more flexible program phase analysis. Journal of Instruction Level Parallelism, 7(4):1–28, 2005.
[5] llvm. GitHub – llvm/llvm-project: The LLVM Project is a collection of modular and reusable compiler and toolchain technologies., Jul 2025.
[6] llvm. llvm machine code analyzer — llvm 22.0.0git documentation-2025, 2025.
[7] S. Na, L. Xumin, and G. Yong. Research on k-means clustering algorithm: An improved k-means clustering algorithm. 2010 Third International Symposium on Intelligent Information Technology and Security Informatics, pp. 63–67, Apr 2010.
[8] S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. ACM SIGARCH Computer Architecture News, 25(2):206–218, May 1997.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98625-
dc.description.abstract為解決大型程式碼分析中所面臨的高昂模擬成本問題,本研究提出一套高效率的效能估算框架,整合 LLVM-MCA、SimPoint,以及兩種資源配置策略:模擬退火(SA)與基於排隊理論的資源分配(QTRA)。當程式規模擴大時,傳統的全追蹤模擬將導致極高的運算時間與資源消耗,因此本研究採用 SimPoint 技術選出具代表性的程式區段,以大幅減少模擬範圍,同時保留原始程式行為的統計特徵。
本方法在 CoreMark 基準測試上進行驗證。實驗結果顯示,QTRA 能產生穩定且具可解釋性的資源配置趨勢,適用於成本敏感與可擴展的設計環境;而 SA 雖能偶爾探索出較佳效能組合,但其隨機特性導致結果波動。最後透過 SimPoint 加權區間估算的週期數與完整 LLVM-MCA 模擬結果相比,其誤差僅約在 -0.75% 至 -8.51% 之間,證實其在大規模程式分析中具有準確性與效率兼具的優勢。本研究提供一種針對大型程式之微架構設計與分析的可行方法,有效降低模擬負擔。
zh_TW
dc.description.abstractTo address the high simulation overhead associated with large-scale program analysis, this study proposes an efficient performance estimation framework that integrates LLVM-MCA, SimPoint, and two resource configuration strategies: Simulated Annealing (SA) and Queueing-Theory-based Resource Allocation (QTRA). As program size increases, traditional full-trace simulation becomes computationally infeasible due to excessive runtime and resource usage. Therefore, this work leverages SimPoint to identify representative program intervals, significantly reducing the simulation scope while preserving the statistical characteristics of the original execution behavior.
The proposed framework is validated using the CoreMark benchmark. Experimental results show that QTRA produces stable and interpretable resource allocation trends, making it suitable for cost-sensitive and scalable architectural design. In contrast, SA can occasionally discover better-performing configurations, but its stochastic nature introduces variability. Finally, when comparing SimPoint-based cycle estimates with full-trace LLVM-MCA simulation, the observed error ranges from -0.75% to -8.51%, confirming the effectiveness and accuracy of this method for large-scale program analysis. Overall, this study provides a practical and efficient approach for microarchitectural optimization under resource constraints.
en
dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-18T01:07:38Z
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dc.description.provenanceMade available in DSpace on 2025-08-18T01:07:38Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontentsVerification Letter from the Oral Examination Committee i
Acknowledgements iii
摘要 v
Abstract vii
Contents ix
List of Figures xi
List of Tables xiii
Chapter 1 Introduction 1
Chapter 2 Background 3
2.1 LLVM 3
2.2 LLVM-MCA 4
2.3 QEMU 5
2.4 SimPoint 5
2.4.1 Basic Block Vector (BBV) 6
2.4.2 K-means Clustering 6
2.5 Importance of Dispatch Size and Program Resources 7
2.6 Simulated Annealing 8
Chapter 3 Methodology 11
3.1 Framework Overview 11
3.2 Interval Clustering and Selection 12
3.3 Dynamic Trace Collection 13
3.4 LLVM-MCA Bottleneck Simulation 14
3.4.1 Memory Cache Assumptions 15
3.4.2 Simulated Annealing (SA) 16
3.4.3 Queueing-Theory-Based Resource Allocation (QTRA) 18
3.5 Time Complexity Analysis 20
3.5.1 Brute Force Search (BFS) 21
3.5.2 Simulated Annealing (SA) 21
3.5.3 Queueing-Theory-Based Resource Allocation (QTRA) 22
3.5.4 Complexity Comparison Summary 23
Chapter 4 Evaluation 25
4.1 Experimental Setup 25
4.2 Resource Cost and Interval Weight 26
4.3 Evaluation Results 27
4.3.1 Evaluation of Resource-Efficient Fronts 27
4.3.2 Comparison of QTRA and SA Results 29
4.3.3 Performance Accuracy: Estimated Cycles of Full vs. SimPoint SA 29
Chapter 5 Future Work 33
Chapter 6 Conclusion 35
References 37
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dc.language.isoen-
dc.subjectSimpointzh_TW
dc.subjectLLVM-MCAzh_TW
dc.subject處理器資源調整zh_TW
dc.subjectProcessor Resource Tuningen
dc.subjectLLVM-MCAen
dc.subjectSimpointen
dc.title基於 SimPoint/LLVM-MCA 效能分析的排隊理論資源分配方法zh_TW
dc.titleQueueing Theory-Based Resource Allocation based on our SimPoint/LLVM-MCA Performance Analysisen
dc.typeThesis-
dc.date.schoolyear113-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee盧瑞山;洪士灝;李逸元zh_TW
dc.contributor.oralexamcommitteeRuei-Shan Lu;Shih-Hao Hung;Yi-Yuan Leeen
dc.subject.keywordLLVM-MCA,Simpoint,處理器資源調整,zh_TW
dc.subject.keywordLLVM-MCA,Simpoint,Processor Resource Tuning,en
dc.relation.page38-
dc.identifier.doi10.6342/NTU202503193-
dc.rights.note未授權-
dc.date.accepted2025-08-11-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept資訊網路與多媒體研究所-
dc.date.embargo-liftN/A-
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