基於微環共振器的晶片訊號傳輸上考慮交叉的光電共同設計

Abstract

隨著低功耗異質整合需求的日益增長，光電互連技術備受關注，而波長路由光網路晶片（wavelength-routed optical network-on-chips, WRONoCs）憑藉其低延遲、低功耗和高頻寬的光訊號傳輸特性，已成為一種極具潛力的解決方案。先前的光電共同設計方法並未考慮基於微環共振器（microring resonator, MRR）的波長路由光網路晶片，而先前基於微環共振器的波長路由光網路晶片拓撲和實體共同設計方法由於整數線性規劃公式的運行時間過長或光學資源佔用過多，導致其在電子設計方面缺乏擴展性。 為了彌補這些缺陷，我們提出了第一個基於微環共振器的晶片訊號傳輸的光電共同設計流程，旨在有效地降低功耗。基於我們提出可擴展的波長路由光網路晶片拓撲構建模組（topology building blocks, TBBs），我們提出了一種新穎的基於二分圖的微環共振器線路分群演算法，以減少光學資源佔用；一種考慮交叉的基於動態規劃的拓撲構建演算法，以有效地最小化交叉交換元件（crossing switching element）的數量；以及一種高效的基於拓撲構建模組的波長分配演算法，無需整數線性規劃。 實驗結果表明，我們的方法在功耗方面顯著優於當前最佳的技術。

Optical-electrical (O-E) interconnects have drawn significant attention as the need for low-power heterogeneous integration grows, and wavelength-routed optical network-on-chips (WRONoCs) have emerged as a promising solution due to their low-delay, low-power, and high-bandwidth optical signal transmissions. Previous O-E codesign methods do not consider microring resonator (MRR)-based WRONoCs, and previous MRR-based WRONoC topological and physical codesign methods lack the scalability for electrical designs due to the prohibitive runtimes of integer linear programming (ILP) formulations or excessive optical resource usages. To remedy these drawbacks, we propose the first O-E codesign flow for MRR-based on-chip signal transmissions to minimize power consumption with high efficiency. Based on our proposed scalable WRONoC topology building blocks (TBBs), we propose a novel bipartite graph-based net clustering algorithm for MRRs to reduce optical resource usage, a crossing-aware dynamic programming-based TBB construction algorithm to effectively minimize the number of crossing switching elements, and an efficient TBB-based wavelength assignment algorithm without an ILP. Experimental results show that our work significantly outperforms state-of-the-art work in power consumption.