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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98481完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡璧合 | zh_TW |
| dc.contributor.advisor | Pi-Ho Hu | en |
| dc.contributor.author | 李庚倫 | zh_TW |
| dc.contributor.author | Geng-Lun Li | en |
| dc.date.accessioned | 2025-08-14T16:17:01Z | - |
| dc.date.available | 2025-08-15 | - |
| dc.date.copyright | 2025-08-14 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-01 | - |
| dc.identifier.citation | [1] C. C. Wu et al., "High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme," 2010 International Electron Devices Meeting, San Francisco, CA, 2010, pp. 27.1.1-27.1.4.
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Jung, "SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 1567-1571, March 2022. [8] Y. Osada et al., "3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications," in IEEE Journal of Solid-State Circuits, vol. 60, no. 3, pp. 1113-1121, March 2025. [9] E. Simoen, B. Dierickx, L. Warmerdam, J. Vermeiren and C. Claeys, "Freeze-out effects on NMOS transistor characteristics at 4.2 K," in IEEE Transactions on Electron Devices, vol. 36, no. 6, pp. 1155-1161, June 1989. [10] S. Bonen et al., "Cryogenic Characterization of 22-nm FDSOI CMOS Technology for Quantum Computing ICs," in IEEE Electron Device Letters, vol. 40, no. 1, pp. 127-130, Jan. 2019. [11] W. . -C. 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M. van Santen, S. Thomann, G. Pahwa, Y. S. Chauhan and H. Amrouch, "Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 8, pp. 3089-3102, Aug. 2023. [17] Y. Hu et al., "Cryo-CMOS Model-Enabled 8-Bit Current Steering DAC Design for Quantum Computing," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 3413-3417. [18] G. Kiene, A. G. Sreenivasulu, R. W. J. Overwater, M. Babaie and F. Sebastiano, "Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC," ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), Milan, Italy, 2022, pp. 53-56. [19] A Miniature 10MHz-3GHz Sub 1-dB NF Cryogenic Inductorless Noise-Canceling Low-Noise Amplifier for Qubit Readout," 2023 IEEE/MTT-S International Microwave Symposium - IMS 2023, San Diego, CA, USA, 2023, pp. 668-671. [20] P. Wang, X. Peng, W. Chakraborty, A. I. Khan, S. Datta and S. Yu, "Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 38.5.1-38.5.4. [21] W. -C. Wang et al., "Cool-CIM: Cryogenic Operation of Analog Compute-In-Memory for Improved Power-efficiency," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4. [22] A. D. Gaidhane, R. Saligram, W. Chakraborty, S. Datta, A. Raychowdhury and Y. Cao, "Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 9, no. 2, pp. 108-115, Dec. 2023. [23] J. Van Houdt, "Memory technology for the terabit era: From 2D to 3D," 2017 Symposium on VLSI Technology, Kyoto, Japan, 2017, pp. T24-T25. [24] M.Manimaraboopathy, M. (2013). Column decoder using PTL for memory. IOSR Journal of Electronics and Communication Engineering, 5, 7-14. [25] Rakshith Saligram, Amol Gaidhane, Yu [Kevin] Cao, Suman Datta, and Arijit Raychowdhury. 2024. Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories. In Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED '24). Association for Computing Machinery, New York, NY, USA, 1–6. [26] S. -F. Fang and V. P. -H. Hu, "Stability and Performance Optimization of 6T SRAM Cell at Cryogenic Temperature," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3. [27] Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric, ASAP7: A 7-nm finFET predictive process design kit, Microelectronics Journal, Volume 53, 2016, Pages 105-115. [28] W. Chakraborty et al., "Cryogenic RF CMOS on 22nm FDSOI Platform with Record fT=495GHz and fMAX=497GHz," 2021 Symposium on VLSI Technology, Kyoto, Japan, 2021, pp. 1-2. [29] Dongmoon Min, Ilkwon Byun, Gyu-Hyeon Lee, Seongmin Na, and Jangwoo Kim. 2020. CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '20). Association for Computing Machinery, New York, NY, USA, 449–464. [30] H. -L. Chiang et al., "How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2. [31] C. -H. Chang et al., "Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond," 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 27.1.1-27.1.4. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98481 | - |
| dc.description.abstract | 將互補式金氧半場效電晶體（Complementary Metal-Oxide Semiconductor, CMOS）操作於低溫環境，有助於實現高效能運算（High-Performance Computing, HPC）。然而，如何在低臨界電壓（Vt）設計下維持靜態隨機存取記憶體（Static Random-Access Memory, SRAM）的穩定性仍是一大挑戰。本研究針對低溫6T與8T-SRAM的特性進行系統性分析，並提出優化設計方案，以同時強化其穩定性與操作效能。
對77 K下6T-SRAM單元，本研究提出兩種優化穩定性Vt設計：(1) 標準供應電壓（0.75 V）下之6T-ES（Enhanced Speed）方案，相較於LVT（|Vt| = 0.15 V）設計，可提升3.4倍的讀取靜態雜訊邊界（Read Static Noise Margin, RSNM）；(2) 低電壓（0.4 V）下之6T-LP（Low Power）方案，透過強化上拉電晶體（Pull-Up, PU）設計，可提升讀取穩定性，同時不犧牲讀取速度與寫入能力。於關鍵製程角落（Process Corner）下，6T-LP可將RSNM提升至LVT設計的1.3倍。 本研究亦分析低溫電流閂鎖感測放大器（Current-Latched Sense Amplifier, CLSA）與電壓閂鎖感測放大器（Voltage-Latched Sense Amplifier, VLSA）。考量冷卻能量（Cooling Energy）後，77 K下CLSA與VLSA皆採用較低的VDD（0.4 V）與LVT設計，CLSA可維持與室溫操作相當的能量效率（Energy Delay Product, EDP），而VLSA則因具備顯著的速度提升，可進一步降低約20%的EDP。 8T-SRAM單元由於具備讀寫路徑分離架構，本身具有較佳的讀取穩定性，本研究進一步提出Vt設計策略，優化其在低VDD（0.4 V）下的穩定性與讀取效能。針對77 K下6N2P與4N4P架構，分別提出8T-6N2P-LP與8T-4N4P-LP之Vt設計方案。相較於採用LVT設計之6T-SRAM，8T-6N2P-LP與8T-4N4P-LP在關鍵製程角落下之RSNM可提升6.3倍。此外，將4N4P讀出電路 (Readout Circuit) 之供應電壓（VSEN）由0.4 V降低至0.3 V（LRV-8T-4N4P-LP），可額外縮短8%的讀取時間。綜合上述研究成果，本論文提出之設計策略展現具備提升低溫SRAM應用於HPC系統之潛力，為未來低溫積體電路設計提供重要參考依據與實用方法。 | zh_TW |
| dc.description.abstract | Cryogenic complementary metal-oxide semiconductor (Cryo-CMOS) technology offers promising potential for enabling high-performance computing (HPC). However, maintaining the stability of static random-access memory (SRAM) under low threshold voltage (Vt) design remains a significant challenge. This study systematically analyzes the characteristics of 6T and 8T-SRAM under cryogenic operation and proposes optimized design strategies to simultaneously enhance both stability and performance.
For 6T-SRAM at 77 K, two Vt optimization designs are proposed: (1) the 6T-ES (Enhanced Speed) design for nominal VDD = 0.75 V, which improves the read static noise margin (RSNM) by 3.4× compared to the LVT design (|Vt| = 0.15 V). (2) the 6T-LP (Low Power) design for reduced VDD = 0.4 V, which strengthens the pull-up (PU) transistors to enhance read stability without sacrificing read and write capability. Under critical process corners, the 6T-LP achieves up to 1.3× RSNM improvement over the LVT baseline. In addition, this study evaluates the performance of cryogenic current-latched sense amplifier (CLSA) and voltage-latched sense amplifier (VLSA). Considering cooling energy, CLSA and VLSA adopt low VDD (0.4 V) and LVT design at 77 K. The cryogenic CLSA maintains a comparable energy delay product (EDP) to its room-temperature counterpart, while the cryogenic VLSA achieves approximately 20% lower EDP due to significant speed improvement. Owing to the decoupled read/write paths, 8T-SRAM inherently provides better read stability. This work proposes Vt design strategies for 6N2P and 4N4P 8T-SRAM to optimize their stability and read performance under low VDD (0.4 V) conditions. Compared to 6T-SRAM with an LVT design at 77 K, the proposed 8T designs enhance RSNM by up to 6.3× under critical process corners. Furthermore, reducing the supply voltage (VSEN) of 4N4P readout circuit from 0.4 V to 0.3 V (LRV-8T-4N4P-LP) shortens the read time by an additional 8%. In summary, the proposed design strategies significantly enhance the stability and performance of cryogenic SRAM, demonstrating strong potential for HPC applications and providing valuable guidance for future cryogenic IC design. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-14T16:17:01Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-14T16:17:01Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 I
摘要 II ABSTRACT IV 目次 VI 圖次 IX 表次 XVII 第一章 導論 1 1.1 背景與相關研究 1 1.1.1 低溫金氧半場效電晶體 (Cryo-CMOS) 3 1.1.2 靜態隨機存取記憶體 8 1.1.3 靜態隨機存取記憶體周邊電路 10 1.2 研究動機 12 1.3 論文架構 13 第二章 6T與8T靜態隨機存取記憶體之操作與模擬方法 14 2.1 前言 14 2.2 6T靜態隨機存取記憶體 (6T-SRAM) 電路介紹 15 2.3 8T靜態隨機存取記憶體 (8T-SRAM) 電路介紹 18 2.4 靜態隨機存取記憶體穩定性指標 21 2.4.1 讀取靜態雜訊邊界 21 2.4.2 寫入邊界 23 2.5 靜態隨機存取記憶體效能指標 24 2.5.1 讀取時間 (Cell Read Access Time) 24 2.5.2 寫入時間 (Time to Write) 26 2.5.3 靜態與動態功率 (Static and Dynamic Power) 28 2.5.4 能量延遲乘積 (Energy Delay Product, EDP) 30 2.6 感測放大器架構與操作方式 31 2.7 元件電性校準與低溫元件特性 35 第三章 77 K下6T靜態隨機存取記憶體分析與優化 40 3.1 前言 40 3.2 6T-SRAM金屬導線電阻電容 41 3.3 77 K下6T靜態隨機存取記憶體單元臨界電壓設計分析 43 3.4 77 K下高效能6T靜態隨機存取記憶體單元臨界電壓設計分析 46 3.5 77 K下低功耗6T隨機存取記憶體單元之臨界電壓設計分析 50 3.5.1 臨界電壓配置對穩定性影響之分析 51 3.5.2 考慮製程變異度之臨界電壓配置比較 54 3.6 77 K下感測放大器效能分析 58 3.7 結論 63 第四章 77 K下8T靜態隨機存取記憶體分析與優化 65 4.1 前言 65 4.2 8T-SRAM金屬導線電阻電容 67 4.3 77 K下8T靜態隨機存取記憶體單元臨界電壓設計與優化 69 4.4 77 K下8T靜態隨機存取記憶體單元考慮製程變異度之分析 72 4.5 8T靜態隨機存取記憶體之讀取電路供應電壓優化設計 77 4.6 結論 81 第五章 總結 83 參考文獻 85 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 低溫金氧半場效電晶體 | zh_TW |
| dc.subject | 靜態隨機存取記憶體 | zh_TW |
| dc.subject | 高效能運算 | zh_TW |
| dc.subject | 臨界電壓 | zh_TW |
| dc.subject | 感測放大器 | zh_TW |
| dc.subject | 能量效率 | zh_TW |
| dc.subject | HPC | en |
| dc.subject | Cryo-CMOS | en |
| dc.subject | energy efficiency | en |
| dc.subject | sense amplifier | en |
| dc.subject | threshold voltage | en |
| dc.subject | SRAM | en |
| dc.title | 6T與8T鰭式場效電晶體之低溫靜態隨機存取記憶體最佳化 | zh_TW |
| dc.title | Optimization of 6T and 8T FinFET Cryogenic SRAM | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 胡振國;黃柏蒼 | zh_TW |
| dc.contributor.oralexamcommittee | Jenn-Gwo Hwu;Po-Tsang Huang | en |
| dc.subject.keyword | 低溫金氧半場效電晶體,靜態隨機存取記憶體,高效能運算,臨界電壓,感測放大器,能量效率, | zh_TW |
| dc.subject.keyword | Cryo-CMOS,SRAM,HPC,threshold voltage,sense amplifier,energy efficiency, | en |
| dc.relation.page | 88 | - |
| dc.identifier.doi | 10.6342/NTU202502990 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-08-05 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2030-07-30 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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