應用於毫米波頻段雙調頻電壓控制振盪器與注入鎖定倍頻器設計

Abstract

本論文提出操作於毫米波頻段之第六代通訊關鍵子電路，包括振盪器與倍頻器。振盪器產生系統所需之本地振盪訊號供鎖相迴路、收發機等系統使用，接著使用倍頻器將前者訊號進一步倍頻至目標頻段。兩者皆為發射機之重要子電路。 本篇一共實作了兩個電路。第一顆晶片運用40奈米製程實作操作於六百六十億至八百二十億赫茲之具備粗調、細調等功能之交叉耦合電壓控制振盪器。本電路透過三圈電感形成之變壓器互感的特性，調整振盪腔之等效電感值，進而影響振盪頻率以達成調頻之目的。此外，電晶體之Body端接上Poly電阻可透過deep-n-well讓p-well浮接，如此一來可隔絕source和body端之通道以些許提升相位雜訊之效能。本晶片之核心面積為0.079平方毫米、整體功耗為7.8毫瓦特，頻率可調範圍為21.6 %，在一千萬赫茲頻率偏移處之相位雜訊為-114.3 dBc/Hz，同樣偏移處考量調頻範圍之品質因數為-189.4 dBc/Hz。 第二顆晶片同樣運用40奈米製程實作使輸出頻率接近或超越使用製程之最大振盪頻率的毫米波注入鎖定倍頻器。過往的注入鎖定三倍頻器因架構中的注入鎖定振盪器，需使之直接操作於目標頻率，但此操作受限於製程最大振盪頻率，因此本電路透過電感耦合注入訊號至環形振盪器，採用三推式架構將輸入頻提高至三倍頻，使注入鎖定結構倍頻器的輸出頻率不再受製程限制。本晶片之核心面積為0.124平方毫米，而功耗為34.2毫瓦特。雖完整電磁模擬上可觀測到三倍頻強度比基頻高之頻率點，但量測上未能找到該類頻率點，故難以定義鎖定範圍和諧波抑制比。但透過注入鎖定輸入訊號至環形振盪器可得相位雜訊於一百萬赫茲的位移為-112.52 dBc/Hz，而於一千萬赫茲的位移之相位雜訊為-121.71 dBc/Hz，在注入鎖定後各有超過40 dB和15 dB之提升。

This thesis proposes sub-circuits for sixth-generation (6G) communication, including an oscillator and a frequency multiplier. The oscillator generates the local oscillation signal required by systems, such as phase-locked loop (PLL) and transceiver (TRX). Subsequently, the frequency of this signal can be levitated to the desired level through a frequency multiplier. Both circuits are crucial sub-circuits of transmitter (TX). In this thesis, two circuits have been designed and implemented. The first chip is a 66 – 82 GHz cross-coupled voltage-controlled oscillator (VCO) with coarse-tuning and fine-tuning fabricated in 40 nm TSMC CMOS process. This circuit employs a three-coil inductor as a transformer to adjust the equivalent inductance of resonant tank, allowing tuning of the oscillation frequency. Furthermore, poly resistors are connected to the body of transistors to create floating p-wells with the assistance of deep-n-wells (DNWs), isolating source and body channels to slightly improve the phase noise (PN). The core area of this chip is 0.079 mm2, and the total power consumption is 7.8 mW. The frequency tuning ratio (FTR) of this chip is 21.6 %. The PN at the 10 MHz offset is -114.3 dBc/Hz, and the FTR-inclusive figure of merit (FoMT) at the same offset is -189.4 dBc/Hz. The second circuit, which also using 40 nm TSMC CMOS process, is an injection-locked frequency multiplier (ILFM) whose frequency of output signal is near or beyond the maximum oscillation frequency (f_max) of applied process technology. Previous designs of ILFMs required the injection-locked oscillator (ILO) to directly operate at three times the fundamental frequency, which is limited by the f_max of the process. This circuit, however, utilizes the triple-push topology to make frequency of output signal exceed f_max without limitations, with the input injection signal inductively coupled to the ring oscillator. The core area of this chip is 0.124 mm2, and the total power consumption is measured to be 34.2 mW. Although frequencies where the power of third harmonic is stronger than the fundamental tone can be observed during the full-EM simulation, such frequency points cannot be found during the measurement. Consequently, it is difficult to define the locking range and harmonic rejection ratio (HRR) based on the measurement results. However, the PN is significantly enhanced by injecting signal to ring oscillator, achieving injection locking. The PN is -112.52 dBc/Hz at the 1 MHz offset and -121.71 dBc/Hz at the 10 MHz offset, showing improvements of over 40 dB and 15 dB respectively.