氮化矽層對提升SOI元件抗總電離劑量效應能力之研究

Abstract

近年來，隨著航太科技的進步、低軌衛星通訊的快速發展，以及核能、國防與高可靠性電子系統的廣泛推廣，電子元件在輻射環境中穩定運作的需求日益殷切。在各類輻射效應中，總電離劑量效應（Total Ionizing Dose, TID）是最常見且最可能造成永久性損傷的一種，會在絕緣層中累積陷阱電荷，進而導致臨界電壓漂移、漏電流上升，甚至造成元件失效。矽覆蓋絕緣層（Silicon-On-Insulator, SOI）技術因具備優異的短通道效應控制能力與低漏電流特性，已廣泛應用於輻射環境。然而，SOI結構中所包含的厚埋氧化層（Buried Oxide, BOX）也使其更容易受到TID的影響，進而引發電性劣化與可靠度問題。 本篇論文提出一種結合多層埋氧化層結構與電子陷阱模型的設計方法，應用於提升SOI元件在總電離劑量效應（TID）下的抗輻射能力。首先，本研究針對單層BOX結構進行分析，探討在不同BOX厚度下通道底部陷阱電荷累積與臨界電壓漂移（ΔVTH）的變化，作為後續結構比較基準。接著，延伸探討SiO2/Si3N4與Si3N4/ SiO2 兩種雙層結構在TID環境中的表現，特別聚焦於Si3N4層中的電子陷阱是否能產生電荷補償效果，以及對ΔVTH抑制的貢獻。最後，本研究進一步分析三層BOX結構SiO2/Si3N4/SiO2在抗TID性能上的改善程度，並總結多層BOX結構設計與電子陷阱機制對於提升SOI元件輻射耐受性的有效性。 研究結果顯示，在單層BOX結構中，ΔVTH並不會隨BOX厚度的減薄而單調下降，反而呈現先上升後下降的趨勢。這表示在某些厚度條件下，BOX底部的電洞會在尚未完全切斷通道底部電力線的情況下更加靠近通道，導致ΔVTH加劇。因此，單純依賴BOX厚度微縮並不足以有效抑制TID效應。在雙層BOX 結構比較中，SiO2/Si3N4結構的ΔVTH減少幅度達30.8%，明顯優於Si3N4/SiO2結構僅有的7.5%，顯示材料排列順序對電場分佈與電荷補償效果具有顯著影響，可有效提升SOI元件在輻射環境下的穩定性與可靠度。而在三層結構方面，於BOX厚度為10 nm的條件下，採用SiO2/Si3N4/SiO2並考慮電子陷阱後，其ΔVTH相較於傳統單層SiO2結構進一步降低45.2%，展現出最佳的抗總電離劑量效應能力。

In recent years, with the development of space technology, the rise of low-earth orbit satellite communication, and the growth of nuclear, military, and high-reliability electronic systems, the need for stable electronic devices in radiation environments has become more important. Among various radiation effects, the Total Ionizing Dose (TID) effect is the most common and may cause permanent damage. TID causes trapped charges in the insulator, which leads to threshold voltage shift, leakage current increase, and even device failure. Silicon-On-Insulator (SOI) technology has good short-channel control and low leakage, so it is widely used in radiation environments. However, the Buried Oxide (BOX) layer in SOI makes it more sensitive to TID, and this causes electrical degradation and reliability issues. To address this issue, this work proposes a TID-hardened SOI design using a multi-layer BOX structure integrated with an electron trap model. First, the ΔVTH behavior in single-layer BOX structures is examined under varying BOX thickness. The results show that ΔVTH does not monotonically decrease with thinner BOX. Instead, it increases first and then decreases, suggesting that in certain BOX thicknesses, holes near the BOX/substrate interface can couple more strongly to the channel, worsening ΔVTH . This indicates that BOX thinning alone is insufficient to suppress TID effects. Next, two double-layer BOX structures, SiO2/Si3N4 and Si3N4/SiO2, are analyzed to investigate the impact of material arrangement and the role of electron traps in Si3N4. The SiO2/Si3N4 configuration shows a ΔVTH reduction of 30.8%, which is significantly better than the 7.5% reduction observed in the Si3N4/SiO2 case. This confirms that the order of the dielectric layers affects the electric field distribution and enhances charge compensation. Finally, a triple-layer BOX structure, SiO2/Si3N4/SiO2, is evaluated under a total BOX thickness of 10 nm. With electron traps considered, this configuration achieves a ΔVTH reduction of 45.2% compared to the single-layer SiO2 baseline, demonstrating the best TID resilience among all tested structures. These results confirm that combining multi-layer BOX engineering with trap-assisted charge control is an effective approach to improving TID hardness in SOI devices.