探索氧化物半導體於新世代記憶體技術之應用

Abstract

隨著生成式人工智慧 (Generative AI) 、物聯網 (IoT) 及邊緣運算 (Edge Computing) 等應用之快速發展，運算系統對記憶體頻寬、延遲與能效提出更高要求，傳統記憶體 (如SRAM、DRAM與Flash) 面臨資料傳輸瓶頸與功耗限制，難以兼顧高速性、高密度與製程整合彈性。因此，具備低漏電流、製程溫度低與結構彈性之氧化物半導體 (Oxide Semiconductor, OS) 材料，成為推進新型記憶體元件設計與積層型三維積體電路 (Monolithic 3D Integration Circuits) 之重要候選技術。 本研究針對氧化物半導體於新興記憶體架構中，對兩項具代表性之應用進行改善：一為氧化物半導體整合矽基電晶體之混合式2T0C嵌入式DRAM (eDRAM) ，另一應用為採用氧化物通道之鐵電電晶體(Ferroelectric FET, FeFET)，實現後段製程相容 (BEOL-Compatible) 之三態內容可定址記憶體 (Ternary Content Addressable Memory, TCAM)。本論文建立完整且可靠的元件與電路模擬流程，於科技電腦輔助設計 (Technology Computer-Aided Design, TCAD) 模擬中構建氧化物半導體能量態密度 (Density of State, DOS) 模型，並採用鐵電 Preisach 模型進行研究，透過本論文建立的 TCAD 模擬流程能很好的模擬出氧化物半導體的導通特性，與鐵電材料之極化翻轉現象。 於 2T0C eDRAM 部分，本研究提出垂直通道電晶體 (Vertical Channel Transistor, VCT) 替代傳統薄膜型電晶體 (Thin Film Transistor, TFT) 作為資料寫入端電晶體，配合先進矽基環繞式閘極電晶體，形成具潛力之OS-Si混合式 2T0C eDRAM 架構。研究結果顯示，垂直通道結構可於不增加面積下延長通道長度，有效改善關閉電流以提升資料保存時間 (提升至815.8秒)。相較於傳統 TFT 結構，以VCT組成之OS-Si eDRAM 於73奈米之VCT通道長度下寫入速度可提升74.2%，且記憶體單元面積亦經佈局優化可達20%縮減，展現其於高密度、高資料保存時間嵌入式記憶體應用之潛力。 於 OS FeFET TCAM 部分，本論文首先針對 FeFET 之低臨界電壓 (Low Threshold Voltage, LVT) 偏負的問題進行電性分析，本研究發現當 LVT 為負值時，會導致TCAM匹配線於搜尋操作時，在匹配狀況下仍產生漏電，使搜尋結果易出現判斷錯誤。為改善此問題，提出「調整底部金屬電極功函數」以抬升LVT，並藉由於寫入高臨界電壓 (High Threshold Voltage, HVT) 過程中，施加正偏壓於頂部電極，提升鐵電層極化量，補償提升金屬功函數導致記憶體視窗 (Memory Window, MW) 縮小之影響，使LVT轉正同時維持適當的MW大小。此外，本論文亦評估調整讀取偏壓 (如提升源極電壓) 對臨界電壓之影響。最終，提出兼顧正值的低臨界電壓與低能耗的操作條件。本論文研究數種調整臨界電壓方法應用於TCAM中進行分析，探討不同元件解決方案之搜尋能耗、延遲、搜尋感測範圍與面積。結果顯示，結合功函數調整與頂閘偏壓之方案，在維持面積不增加的前提下，相較於單純提升閘極金屬功函數之方案可提升TCAM搜尋感測範圍達5.4倍，並將搜尋延遲從489 ps降低至104 ps，搜尋能耗僅0.3 fJ，在能耗延遲面積乘積 (Energy Delay Area Product) 的綜合評估中，此方案更是有80%的優化，相較於抬升源極線之方案亦有約50%的進步。 綜合上述，氧化物半導體具備低漏電、高載子遷移率與低溫製程等優勢，配合本研究所提出之元件設計與操作優化策略，能有效突破傳統記憶體於效能、密度與整合性方面之瓶頸。本論文所提出之垂直通道電晶體作為OS-Si混合式eDRAM，與調整閘極金屬功函數結合頂閘寫入輔助偏壓實現氧化物半導體通道FeFET於TCAM之應用方案，提供未來以氧化物半導體作為記憶體應用之具體路徑，實現可堆疊、高效能、低功耗之下一世代記憶體與記憶體內運算架構。

With the rapid advancement of emerging applications such as Generative Artificial Intelligence (AI), the Internet of Things (IoT), and Edge Computing, modern computing systems demand higher memory bandwidth, lower latency, and improved energy efficiency. Traditional memory technologies—including SRAM, DRAM, and Flash—are increasingly constrained by data transfer bottlenecks and power consumption, making it difficult to simultaneously achieve high speed, high density, and process integration flexibility. In this thesis, oxide semiconductors (OS), which feature low leakage current, low-temperature processing, and structural flexibility, have emerged as promising candidates for the development of next-generation memory devices and monolithic 3D (M3D) integration circuits. This study explores two representative oxide semiconductor-based memory architectures: (1) a hybrid 2T0C embedded DRAM (eDRAM) that integrates oxide semiconductors with silicon-based transistors, and (2) a BEOL-compatible ternary content-addressable memory (TCAM) utilizing FeFETs with oxide semiconductor channels. To support these developments, a comprehensive simulation methodology was established. The oxide semiconductor’s density-of-state (DOS) model and the ferroelectric Preisach model were implemented in Sentaurus Technology Computer-Aided Design (TCAD) to accurately analyze the conduction behavior of OS materials and polarization switching in ferroelectrics. In the 2T0C eDRAM design, a vertical channel transistor (VCT) is proposed to replace the conventional thin-film transistor (TFT) as the write-access device. Combined with an advanced silicon-based gate-all-around (GAA) transistor, the proposed OS-Si hybrid structure enhances memory characteristics. Simulation results indicate that the vertical structure allows for a longer channel length design without area penalty, significantly reducing off-state leakage current and improving data retention time up to 815.8 seconds. Compared to the TFT-based design, the VCT-based OS-Si eDRAM shows a 74.2% improvement in write speed at a 73 nm channel length and achieves a 20% area reduction through layout optimization, demonstrating its potential in high-density and high-retention embedded memory applications. For the OS FeFET-based TCAM, this thesis addresses the issue of negative low-threshold voltage (LVT), which causes undesired leakage on match lines and leads to search errors. To resolve this, an approach of tuning the bottom metal gate work function to raise the LVT and applying a positive top-gate voltage during HVT (high threshold voltage) programming to enhance ferroelectric polarization is proposed. This compensates for the memory window (MW) degradation caused by metal work function increment. Additionally, the effect of read bias tuning (e.g., raised source voltage (VSS)) on threshold voltage was evaluated. The final operating condition balances the positive LVT demand and energy efficiency. By implementing these threshold voltage adjustment strategies in TCAM arrays, the search energy, latency, sensing margin, and footprint were comprehensively analyzed. Results show that the proposed method—metal work function tuning with top-gate assisted HVT programming—achieves a 5.4× increase in sensing margin and reduces search latency from 489 ps to 104 ps, with only 0.3 fJ search energy. The energy-delay-area product (EDAP) is improved by 80%, with a ~50% advantage over schemes using VScL raising. In summary, oxide semiconductors offer advantages in ultra-low leakage current, high mobility, and low-temperature processing. When utilized with the device architecture and operation strategies proposed in this work, they can effectively overcome limitations in performance, density, and integration faced by traditional memory. The demonstrated approaches—VCT-enabled OS-Si hybrid eDRAM and polarization-assisted FeFET TCAM with work function tuning—provide a concrete path toward realizing stackable, high-performance, low-power memory and in-memory computing architectures for next-generation systems.