金氧半元件氧化矽捕陷效應對記憶行為之影響

Abstract

本研究針對金氧半穿隧二極體在反轉操作區域中的記憶體行為進行探討，重點聚焦於氧化層中氧化層電荷對電性特性與記憶效應的影響。為了因應高速運算與類神經突觸應用對新型非揮發性記憶體的需求，本研究以陽極氧化方式在 p 型矽基板上成長不同厚度之二氧化矽介電層，探討金氧半穿隧二極體中電子捕陷現象與其對記憶機制的影響。實驗中，施加負偏壓定電壓應力可使電子注入並捕陷於介電層中，形成局部負電荷區域與內部電場。這些捕陷電荷會有效抑制由閘極外部氧化層中氧化電荷所吸引而來的反轉電子橫向流入，導致反轉區電流下降，以及捕陷電荷會阻礙由反轉電子所形成的側向導電通道導通，也因此RC等效電路無法有效地側向傳導交流訊號至外部，使得外部的空乏區電容無法讀取到，進而導致讀取時得到的電容值下降，反轉電容頻率響應消失。而當施加正偏壓定電壓應力後，捕陷電子被釋放，元件的電流與電容特性恢復至初始狀態，展現出可逆之雙態記憶效應。為驗證此記憶行為源自閘極外部氧化層電荷的作用，設計平面型元件與去除外圍氧化層的元件進行比較實驗。結果顯示，去除外圍氧化層的元件在負偏壓定電壓應力後無電流衰退現象，證實外部氧化電荷吸引的反轉電子為記憶現象之主因。進一步透過暫態電流量測，觀察電子去捕陷的時間動態，並探討不同介電層厚度與負偏壓定電壓應力強度對捕陷行為的影響。分析結果顯示，介電層越厚，須施加越強的電場，才能使電子有效捕陷至靠近矽/氧化層介面處，產生足夠強度之內部電場以驅動記憶切換。最後，透過比較不同金屬閘極半徑的元件，進一步分析捕陷電荷在空間中的分布情形。結果顯示，記憶行為所產生的電流變化仍與金屬周長成正比，非與面積成正比，說明電子捕陷發生於整個金屬下方的介電層中，而非僅集中於邊緣區域。綜合上述，本研究成功闡明了氧化層中電荷捕陷效應在MISTD元件記憶行為中的主導角色。此研究成果顯著增進了對基於氧化層電荷捕陷之記憶機制的基礎認識，並展現出MISTD在發展低功耗、非揮發性及可重複擦寫記憶體技術方面之潛力，提供未來基於氧化電荷調控之記憶體元件設計的重要理論依據與實務參考。

This study presents a comprehensive investigation into the memory behavior of Metal–Insulator–Semiconductor Tunnel Diodes (MISTDs) in the inversion operating region, with particular emphasis on the impact of oxide charges and trap effects within the dielectric layer on electrical characteristics and memory behavior. To address the growing demand for novel non-volatile memory solutions in high-speed computing and neuromorphic synapse applications, silicon dioxide layers of varying thicknesses were grown on p-type silicon substrates via anodic oxidation. The objective was to examine how electron trapping within the dielectric layer governs the memory mechanism of MISTDs. Under negative bias stress (NBS), electrons are injected and trapped within the dielectric layer, forming localized regions of negative charge and an associated internal electric field. These trapped charges effectively impede the lateral inflow of inversion electrons that are attracted by oxide charges located outside the gate region, resulting in a noticeable reduction in inversion current. Additionally, the trapped charges hinder the formation of lateral conductive paths established by these inversion electrons. As a result, the RC equivalent circuit cannot efficiently transmit alternating signals laterally to the outer regions, making the external depletion capacitance undetectable. This leads to a decrease in the measured capacitance and the disappearance of the frequency response in inversion region. Conversely, when positive bias stress (PBS) is applied, the previously trapped electrons are released, allowing both current and capacitance characteristics to recover to their initial states. This reversible two-state memory behavior demonstrates the device’s potential for memory applications. To confirm that this memory effect originates from oxide charges external to the gate, comparative experiments were conducted using Planar Devices with and without peripheral oxide layers. Results showed that devices with the outer oxide removed exhibited no degradation in inversion current after NBS, verifying that the inversion electrons induced by the outer oxide charges are primarily responsible for the memory behavior. Further transient current measurements were employed to monitor the temporal dynamics of electron detrapping and to explore the effects of dielectric layer thickness and NBS magnitude on trapping behavior. The analysis revealed that thicker dielectric layers require higher electric fields to enable electron trapping close to the Si/SiO₂ interface, where the resulting internal field is sufficient to drive the memory switching effect. Additionally, by comparing devices with various gate electrode radii, the spatial distribution of trapped electrons was further examined. The findings indicate that the current modulation associated with the memory behavior scales with the perimeter rather than the area of the gate, suggesting that electron trapping occurs beneath the entire gate region rather than being localized only at the edges. The experimental observations and memory mechanism proposed in this study clarify the dominant role of trapping electron in MISTD memory behavior. The insights provided significantly enhance the fundamental understanding of oxide-based charge trapping mechanisms, highlighting their potential for developing low-power, non-volatile, and rewritable memory technologies. This research thus offers essential theoretical and practical foundations for future design and optimization of oxide-charge-controlled memory devices.