具快速負載暫態響應之電容電流定導通時間控制降壓轉換器

Abstract

在邊緣AI運算與可攜式裝置對低功耗與快速暫態響應需求日益提升的趨勢下，直流-直流降壓轉換器的控制架構面臨穩定性與響應速度之間的權衡挑戰。傳統以電容電流為感測基礎的控制雖具備優異的暫態響應能力，卻易受感測電路不匹配影響，導致系統穩定性降低。為解決上述問題，本論文提出兩種以電容電流感測為基礎之改良型定導通時間(Constant On-Time, COT)控制架構，兼顧高速暫態響應與系統穩定性。首先，本論文針對電容電流定導通時間（Capacitor Current Constant On-Time, CCCOT）控制在感測不匹配條件下的穩定性挑戰，提出加入被動斜率補償之改良架構。該設計在僅略微犧牲負載暫態響應的情況下，實現感測器與輸出電容阻抗誤差容忍度達 ±40%。本控制器採用台積電 0.18 μm CMOS 製程實現，晶片面積為 1189 μm × 1199 μm。量測結果顯示，在輸出電壓為 1.1 V、負載電流變化量 1 A、電流變化斜率為 1 A/500 ns 的情況下，電壓下跌僅 42 mV，回復時間為 1 μs，具備優異的暫態性能。進一步地，為解決 CCCOT 架構需以暫態響應犧牲換取穩定性，以及難以穩定操作於不連續導通模式（DCM）之限制，本論文提出雙電容電流積分斜坡定導通時間（Double Capacitor Current Ramp Integrating COT, DCCRICOT）控制架構。該架構透過兩路電容電流感測路徑與積分斜坡調變訊號，不僅保留快速暫態響應特性，亦大幅提升系統穩定性與雜訊容忍度。DCCRICOT 架構可穩定操作於連續與不連續導通模式（CCM/DCM），並在 10 mA–1.1 A 負載範圍內展現穩健性能。此晶片亦以台積電 0.18 μm CMOS 製程實現，晶片面積為 1289 μm × 1199 μm，並導入改良的負載電流變化產生器，可實現 1.1 A/70 ns 的負載電流斜率。實測結果顯示，在負載步階為 1.1 A、電流斜率為 1.1 A/70 ns 的條件下，輸出電壓下跌為 62 mV(偏離理想比率僅 1.9%)，回復時間為 1.6 μs，且系統無不穩定現象，驗證所提架構具備高速與高穩定度之優勢。

With the growing demand for low power consumption and fast transient response in edge AI and portable devices, the control architecture of DC-DC buck converters faces increasing challenges in balancing stability and response speed. Traditional control schemes based on capacitor current sensing offer excellent transient response, but are highly susceptible to sensing mismatch, which compromises system stability. To address this issue, this dissertation proposes two improved constant on-time (COT) control architectures based on capacitor current sensing that jointly enhance both transient speed and stability. First, this work introduces a passive ramp-compensated architecture to improve the stability of the capacitor current constant on-time (CCCOT) control scheme under sensing mismatch. The proposed design achieves tolerance to sensor and capacitor impedance deviations up to ±40%, with only a minor compromise in transient response. Fabricated using TSMC 0.18 μm CMOS technology, the chip occupies an area of 1189 μm × 1199 μm. Measurement results show that under 1.1 V output voltage, a 1 A load step, and a load current slew rate of 1 A/500 ns, the output voltage undershoot is only 42 mV, with a recovery time of 1 μs—demonstrating excellent transient performance. To further resolve the trade-off between transient response and stability and overcome CCCOT’s inability to operate reliably in discontinuous conduction mode (DCM), this dissertation proposes a novel control scheme: Double Capacitor Current Ramp Integrating COT (DCCRICOT). By employing two separate capacitor current sensing paths and an integrated ramp modulation signal, this architecture retains the fast response benefits of CCCOT while significantly improving system stability and noise immunity. The DCCRICOT control scheme supports robust operation in both continuous (CCM) and discontinuous (DCM) conduction modes and demonstrates stable performance across a wide load range from 10 mA to 1.1 A. The chip, also implemented in TSMC 0.18 μm CMOS, occupies 1289 μm × 1199 μm and features an enhanced load current step generator capable of generating a slew rate up to 1.1 A/70 ns. Experimental results show that under a 1.1 A load step with a 1.1 A/70 ns slew rate, the output voltage dip is only 62 mV (with a deviation-from-ideal rate of just 1.9%) and the recovery time is 1.6 μs. No instability was observed, validating the proposed design’s superior speed and stability.