請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97539完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 蘇俊澤 | zh_TW |
| dc.contributor.author | Chun-Tse Su | en |
| dc.date.accessioned | 2025-07-02T16:22:08Z | - |
| dc.date.available | 2025-07-03 | - |
| dc.date.copyright | 2025-07-02 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-06-16 | - |
| dc.identifier.citation | [1] B. Razavi, “Design Considerations for Interleaved ADCs,” IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug. 2013.
[2] C.-Y. Lin, Y.-H. Wei, and T.-C. Lee, “A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique,” IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1508–1517, May 2018. [3] M. Guo, J. Mao, S.-W. Sin, H. Wei, and R. P. Martins, “A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,” IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 693–705, Mar. 2020. [4] M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011. [5] Y. Zhou, B. Xu, and Y. Chiu, “A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector,” IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 920–931, Apr. 2015. [6] D. Li, Z. Zhu, J. Liu, H. Zhuang, Y. Yang, and N. Sun, “A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration,” IEEE Journal of Solid-State Circuits, vol. 55, no. 11, pp. 3051–3063, Nov. 2020. [7] Y. Lim and M. P. Flynn, “A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC,” in 2017 Symposium on VLSI Circuits, Jun. 2017, pp. C98–C99. [8] C.-Y. Hsu and T.-C. Lee, “A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 1, pp. 28–32, Jan. 2025. [9] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq, and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 646–658, Mar. 2019. [10] H.-H. Chang, T.-C. Lin, and T.-C. Lee, “A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, pp. 2021–2025, Apr. 2022. [11] Z. Zheng, L. Wei, J. Lagos, E. Martens, Y. Zhu, C.-H. Chan, J. Craninckx, and R. P. Martins, “A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier,” IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1673–1683, Jun. 2022. [12] Y. Shen, S. Liu, Y. Cao, H. Han, H. Liang, Z. Dong, D. Li, R. Ding, and Z. Zhu, “A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage,” IEEE Journal of Solid-State Circuits, vol. 60, no. 1, pp. 260–271, Jan. 2025. [13] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, Dec. 1994. [14] S. Jamal, D. Fu, M. Singh, P. Hurst, and S. Lewis, “Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 1, pp. 130–139, Jan. 2004. [15] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita, and U.-K. Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2928–2942, Dec. 2012. [16] Y. Lim and M. P. Flynn, “A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers,” IEEE Journal of Solid-State Circuits, vol. 50, no. 10, pp. 2331–2341, Oct. 2015. [17] L. Sumanen, M. Waltari, and K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,” in ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), vol. 1, Dec. 2000, pp. 32–35 vol.1. [18] B. Murmann, “ADC Performance Survey 1997-2024,” Aug. 2024, [Online]. Available: https://github.com/bmurmann/ADC-survey. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97539 | - |
| dc.description.abstract | 本論文提出一款無須校準的十二位元每秒取樣十五億點管線式類比數位轉換器，採用合併子類比數位轉換器量化技術。在傳統管線式類比數位轉換器架構的基礎上，所提出的技術延長了放大時間，從而放寬了內部級殘餘放大器的性能要求。
一個以 28 奈米 CMOS 技術製造的原型類比數位轉換器，在奈奎斯特輸入頻率下達到 70.52 分貝的無贅餘失真的動態範圍以及 58.03 分貝的訊號對雜訊失真比，並在 1 伏特供應電壓下消耗 18.5 毫瓦的功率。其 Schreier 和 Walden 效能指標分別達到 164.1 分貝以及 18.9 fJ/conversion-step。此外，我們開發了一個雙通道版本，將轉換速率提升至 3 GS/s。 | zh_TW |
| dc.description.abstract | This thesis presents a calibration-free 12-bit 1.5-GS/s pipelined analog-to-digital converter (ADC) employing a merged sub-ADC quantization (MSAQ) technique. Building upon the conventional pipelined ADC architecture, the proposed technique extends the amplification time, thereby relaxing the performance requirements of the inner-stage residue amplifier.
A prototype ADC implemented in a 28-nm CMOS technology achieves an SFDR of 70.52 dB and an SNDR of 58.03 dB at a Nyquist input, while consuming 18.5 mW from a 1-V supply. It yields Schreier and Walden figures of merit (FoM) of 164.1 dB and 18.9 fJ/conv.-step, respectively. Additionally, we developed a two-channel version, boosting the conversion rate to 3 GS/s. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-07-02T16:22:08Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-07-02T16:22:08Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Fundamental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 ADC Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 Bandwidth (BW) . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.2 Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . 6 2.2.3 Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . 7 2.2.4 Signal-to-noise Ratio (SNR) . . . . . . . . . . . . . . . . . . . . 7 2.2.5 Signal-to-noise and Distortion Ratio (SNDR) . . . . . . . . . . . . 7 2.2.6 Effective Number of Bits (ENOB) . . . . . . . . . . . . . . . . . . 7 2.2.7 Spurious Free Dynamic Range (SFDR) . . . . . . . . . . . . . . . . 8 2.2.8 Total Harmonic Distortion (THD) . . . . . . . . . . . . . . . . . . 8 2.2.9 Dynamic Range (DR) . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.10 Figure-of-merit (FoM) . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Introduction of ADC Architecture . . . . . . . . . . . . . . . . . . 9 2.3.1 Conventional Pipelined ADC . . . . . . . . . . . . . . . . . . . . 9 2.3.2 Time-interleaved ADC . . . . . . . . . . . . . . . . . . . . . . . 11 3 System Architecture And Implementation . . . . . . . . . . . . . . . . 15 3.1 Merged Sub-ADC Quantization Technique . . . . . . . . . . . . . . . . 15 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 Chip 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 Multiplying DAC . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.3 3-bit Flash Backend Circuit . . . . . . . . . . . . . . . . . . . . 24 3.2.4 Chip 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 Ring Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 Slewing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.2 Stabilization State . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3 Steady State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.4 Nested Ring Amplifier . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 Peripheral Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 Bootstrapped Switch . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.5 Synchronization, Decimation and Output Buffer . . . . . . . . . . . 32 3.5 Layout Floor Plan and Simulation Results . . . . . . . . . . . . . . . 34 4 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1 Chip Micrograph . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 Printed Circuit Board Designed . . . . . . . . . . . . . . . . . . . . 38 4.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.1 Fundamental Setup . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3.2 Phase Unbalance of Transformer . . . . . . . . . . . . . . . . . . . 41 4.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.1 Chip 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.2 Chip 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 | - |
| dc.language.iso | en | - |
| dc.subject | 管線式類比數位轉換器 | zh_TW |
| dc.subject | 單通道 | zh_TW |
| dc.subject | 無須校準 | zh_TW |
| dc.subject | 環形放大器 | zh_TW |
| dc.subject | 合併子類比數位轉換器量化技術 | zh_TW |
| dc.subject | merged sub-ADC quantization (MSAQ) | en |
| dc.subject | single channel | en |
| dc.subject | pipelined ADC | en |
| dc.subject | calibration-free | en |
| dc.subject | ring amplifier | en |
| dc.title | 一個採用合併子類比數位轉換器量化技術之十二位元每秒取樣十五億點管線式類比數位轉換器 | zh_TW |
| dc.title | A 12b 1.5GS/s Pipelined ADC with a Merged Sub-ADC Quantization Technique | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;林宗賢;鍾勇輝 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tsung-Hsien Lin;Yung-Hui Chung | en |
| dc.subject.keyword | 管線式類比數位轉換器,合併子類比數位轉換器量化技術,環形放大器,無須校準,單通道, | zh_TW |
| dc.subject.keyword | pipelined ADC,merged sub-ADC quantization (MSAQ),ring amplifier,calibration-free,single channel, | en |
| dc.relation.page | 53 | - |
| dc.identifier.doi | 10.6342/NTU202501127 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-06-16 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2030-06-12 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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