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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模 | zh_TW |
| dc.contributor.advisor | Chien-Mo Li | en |
| dc.contributor.author | 廖政毓 | zh_TW |
| dc.contributor.author | Jeng-Yu Liao | en |
| dc.date.accessioned | 2025-04-07T16:10:28Z | - |
| dc.date.available | 2025-04-08 | - |
| dc.date.copyright | 2025-04-07 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-02-13 | - |
| dc.identifier.citation | [1] H. H. Chen, S.-H. Kuo, J. Tung, and M. C.-T. Chao, “Statistical techniques for predicting system-level failure using stress-test data,” in 2015 IEEE 33rd VLSI Test Symposium (VTS), pp. 1–6, 2015.
[2] C. Chen, J.-Y. Liao, J. C.-M. Li, H. H. Chen, and E. J.-W. Fang, “Vmin prediction using nondestructive stress test,” in 2023 IEEE 41st VLSI Test Symposium (VTS), pp. 1–7, 2023. [3] H. H. Chen, “Analysis of vmin variability in complex digital logic via post-silicon profiling,” in 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), pp. 1–4, 2023. [4] W.-C. Lin, C. Chen, C.-H. Hsieh, J. C.-M. Li, E. J.-W. Fang, and S. S.-Y. Hsueh, “Ml-assisted vminbinning with multiple guard bands for low power consumption,” in 2022 IEEE International Test Conference (ITC), pp. 213–218, 2022. [5] S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,” IEEE Micro, vol. 25, no. 6, pp. 10–16, 2005. [6] O. S. Unsal, J. W. Tschanz, K. Bowman, V. De, X. Vera, A. Gonzalez, and O. Ergin, “Impact of parameter variations on circuits and microarchitecture,” IEEE Micro, vol. 26, no. 6, pp. 30–39, 2006. [7] Y.-T.Kuo,W.-C.Lin,C.Chen,C.-H.Hsieh,J.C.-M.Li,E.Jia-WeiFang,andS.S.-Y.Hsueh, “Minimum operating voltage prediction in production test using accumulative learning,” in 2021 IEEE International Test Conference (ITC), pp. 47–52, 2021. [8] A. D. Singh, “Understanding vmin failures for improved testing of timing marginalities,” in 2022 IEEE International Test Conference (ITC), pp. 372–381, 2022. [9] Y. Yin, R. Chen, C. He, and P. Li, “Domain-specific machine learning based minimum operating voltage prediction using on-chip monitor data,” in 2023 IEEE International Test Conference (ITC), pp. 99–104, 2023. [10] J.-Y. Chang and E. McCluskey, “Detecting delay flaws by very-low-voltage testing,” in Proceedings International Test Conference 1996. Test and Design Validity, pp. 367–376, 1996. [11] T. Chen and C. Guestrin, “Xgboost: A scalable tree boosting system,” in Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, KDD ’16, (New York, NY, USA), p. 785–794, Association for Computing Machinery, 2016. [12] F. T. Liu, K. M. Ting, and Z.-H. Zhou, “Isolation forest,” in 2008 Eighth IEEE International Conference on Data Mining, pp. 413–422, 2008. [13] J. H. Holland, “Genetic algorithms,” Scientific American, vol. 267, no. 1, pp. 66–73, 1992. [14] F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion, O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg, et al., “Scikit-learn: Machine learning in python,” the Journal of machine Learning research, vol. 12, pp. 2825–2830, 2011. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97302 | - |
| dc.description.abstract | 我們提出了一種全面的流程，用於透過壓力測試識別高的最小工作電壓晶片並預測最小工作電壓。該方法透過處理壓力測試失敗記錄檔生成名為CSCP的特徵，旨在應對新的測試架構所帶來的挑戰。為了提高預測準確性，我們採用了結合Pearson 相關係數和F回歸的雙階段特徵選擇方法。此外，我們使用遺傳算法來選擇與最小工作電壓相關的特定測試圖樣，大幅縮短測試時間。為了考慮Vmin在多核CPU中的差異，我們應用了多核Vmin模型（多模型）來預測每個核心的Vmin，並應用了單個最差核心Vmin模型（單模型）來預測最差核心的Vmin。
在先進的4nm多核CPU設計上的實驗結果表明，所提出的兩階段方法有效地選擇了不同核心中的重要特徵。此外，我們的方法在高的最小工作電壓晶片識別中實現了超過93%的測試圖樣減少率，在最小工作電壓預測中實現了超過66%的測試圖樣減少率。使測試時間比傳統方法加快了80倍以上。此外，各核最小工作電壓的均方根誤差低至8.30mV，而最差核最小工作電壓的均方根誤差低至7.07 mV 。對於每個核心Vmin預測（使用多模型），平均RMSE低至8.30mV，與單模型相比減少了30%的誤差。同樣，對於最差核心Vmin預測（使用單模型），RMSE低至7.07mV，與多模型相比減少了7.59%的誤差。 | zh_TW |
| dc.description.abstract | We propose a comprehensive method for identifying high Vmin chips and predicting Vmin through stress test. Our approach processes stress-test fail-logs to generate features, known as CSCP, designed to address the challenges of the new scan compression structure. To enhance prediction accuracy, we select important features using a two-phase approach that combines Pearson correlation and F-regression. Additionally, we employ genetic algorithms to select specific test patterns correlated with Vmin, significantly reducing test time. To account for the variation in Vmin across CPU cores, we apply multi-core Vmin model (multi-model) to predict each-core Vmin and apply single worst-core Vmin model (single-model) to predict the worst-core Vmin.
Experimental results on advanced 4nm multi-core CPU designs demonstrate that the proposed two-phase approach effectively select important features across different cores. Our approach achieves over 93% reduction in test patterns for high Vmin chips identification and over 66% reduction in test patterns for Vmin prediction. This approach can save test time by more than 80 times compared to traditional Vmin measurement methods. For each-core Vmin prediction using multi-model, the average RMSE is as low as 8.30 mV, achieving a 30% error reduction compared to the single-model. Similarly, for worst-core Vmin prediction using single-model, the RMSE is as low as 7.07 mV, offering a 7.59% error reduction compared to the multi-model. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-04-07T16:10:28Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-04-07T16:10:28Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements i
摘要 ii Abstract iii Contents v List of Figures viii List of Tables x Chapter1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Proposed Technique . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter2 Background 7 2.1 Stress Onchip-clocktest MismAtch Count(SOMAC) . . . . . . . . . 7 2.2 Previous Work about Chip Performance Prediction . . . . . . . . . . 13 2.3 Correlation for Feature Selection. . . . . . . . . . . . . . . . . . . . 16 2.3.1 Pearson Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 Spearman Correlation . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.3 F-regression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Regression Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.1 Linear regression model . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 XGBoost regression model . . . . . . . . . . . . . . . . . . . . . . 21 2.5 IsolationForest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter3 Proposed Technique 24 3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Multi-core SOMAC Data Generation . . . . . . . . . . . . . . . . . 25 3.3 CSCP-Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 High Vmin Chips Identification . . . . . . . . . . . . . . . . . . . . 29 3.3.2 Vmin Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4 Test Pattern Selection. . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 Model Training and Evaluation . . . . . . . . . . . . . . . . . . . . 36 3.5.1 High Vmin Chips Identification . . . . . . . . . . . . . . . . . . . . 36 3.5.2 Vmin Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter4 Experimental Results 39 4.1 Experimental Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 High Vmin Chips Identification . . . . . . . . . . . . . . . . . . . . . 40 4.3 Vmin Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4 Single-model and Multi-model Comparison . . . . . . . . . . . . . . 45 4.5 Estimated Test Time . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter5 Discussion 49 5.1 Diagnostic Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 PrimeTime STA analysis . . . . . . . . . . . . . . . . . . . . . . . . 50 Chapter 6 Conclusion 52 References 54 | - |
| dc.language.iso | en | - |
| dc.subject | 非破壞性壓力測試 | zh_TW |
| dc.subject | 晶片效能預測 | zh_TW |
| dc.subject | Chip performance prediction | en |
| dc.subject | Nondestructive stress test | en |
| dc.title | 使用SOMAC預測多核處理器的最小工作電壓以及最差核的最小工作電壓 | zh_TW |
| dc.title | Multi core Vmin and Worst core Vmin prediction using SOMAC | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃俊郎;陳海力 | zh_TW |
| dc.contributor.oralexamcommittee | Jiun-Lang Huang;Harry H. Chen | en |
| dc.subject.keyword | 晶片效能預測,非破壞性壓力測試, | zh_TW |
| dc.subject.keyword | Chip performance prediction,Nondestructive stress test, | en |
| dc.relation.page | 56 | - |
| dc.identifier.doi | 10.6342/NTU202500553 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-02-13 | - |
| dc.contributor.author-college | 重點科技研究學院 | - |
| dc.contributor.author-dept | 積體電路設計與自動化學位學程 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 積體電路設計與自動化學位學程 | |
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