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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97218完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳育任 | zh_TW |
| dc.contributor.advisor | Yuh-Renn Wu | en |
| dc.contributor.author | 陳子皓 | zh_TW |
| dc.contributor.author | Zhi-Hao Chen | en |
| dc.date.accessioned | 2025-02-27T16:43:39Z | - |
| dc.date.available | 2025-02-28 | - |
| dc.date.copyright | 2025-02-27 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-02-17 | - |
| dc.identifier.citation | [1] C. Bolognesi, M. Dvorak, O. Pitts, S. Watkins, and T. MacElwee. Investigation of high-current effects in staggered lineup inp/gaasb/inp heterostructure bipolar transistors: Temperature characterization and comparison to conventional type-i hbts and dhbts. In International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), pages 35–2. IEEE, 2001.
[2] J. Ge, H.-G. Liu, Y.-B. Su, Y.-X. Cao, and Z. Jin. Physical modeling based on hydrodynamic simulation for the design of InGaAs/InP double heterojunction bipolar transistors. Chinese Physics B, 21(5):058501, 2012. [3] E. Harmon, M. L. Lovejoy, M. R. Melloch, M. S. Lundstrom, D. Ritter, and R. Hamm. Minority-carrier mobility enhancement in p+ ingaas lattice matched to inp. Applied physics letters, 63(5):636–638, 1993. [4] E. Iverson, T. Low, B. Wu, M. Iwamoto, and D. D’ Avanzo. Measurement of base transit time and minority electron mobility in gaasb-base inp dhbts. In CS MANTECH Conference. [5] S. S. Li and S. S. Li. High-speed iii–v semiconductor devices. Semiconductor Physical Electronics, pages 455–502, 1993. [6] J. Ouchrif, A. Baghdad, A. Sahel, A. Badri, and A. Ballouk. Improved electrical performances of an inp/ingaas heterojunction bipolar transistor. [7] M. Sotoodeh, A. Khalid, and A. Rezazadeh. Empirical low-field mobility model for iii–v compounds applicable in device simulation codes. Journal of applied physics, 87(6):2890–2900, 2000. [8] T.-H. Yu and K. F. Brennan. Monte carlo calculation of two-dimensional electron dynamics in gan–algan heterostructures. Journal of applied physics, 91(6):3730–3736, 2002. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97218 | - |
| dc.description.abstract | 由於針對 DHBT 元件的模擬研究文獻相對較少,且模擬過程中對合適參數的設定及模擬功能的使用細節通常未被詳細說明,因此本研究採用實驗室開發的二維元件 TCAD 軟體 DDCC(Drift-Diffusion Carrier Controller)進行模擬研究。我們針對 type I 和 type II DHBT 進行元件參數特性模擬、尺寸微縮預測及磊晶結構的設計與優化。
在參數特性檢驗中,我們發現壓降主要集中在 Base 層及 Base-Collector 連接處的空乏層,而其他區域,如重摻雜磊晶層與 Base-Emitter 接面磊晶層,其壓降與阻抗占比較低。在尺寸微縮預測方面,轉導(gm)主要受 Emitter mesa 寬度及 Base-Emitter 電極間距的影響,而電容(C)則與 pn 接面寬度呈正相關,因為寬度與接面面積成正比。微縮後,type I 和 type II 的最佳 fT 值分別約為 140 GHz 和 450 GHz。為了進一步優化 type I DHBT,我們透過減少空乏層及基極磊晶層厚度,成功將 fT 提升至約 300 GHz。最後,我們探討了基極厚度縮小時,type I 和 type II DHBT 元件特性的差異。 | zh_TW |
| dc.description.abstract | Abstract Due to the relatively limited literature on DHBT device simulations and the lack of detailed explanations regarding suitable parameter settings and the use of simulation functions, this study employs the lab-developed two-dimensional TCAD software DDCC (Drift-Diffusion Carrier Controller) for simulation research. We conducted simulations of device parameter characteristics, size scaling predictions, and epitaxial structure design and optimization for type I and type II DHBTs.
In examining parameter characteristics, we found that the voltage drop is primarily concentrated in the base layer and the depletion region at the Base-Collector junction, whereas other areas, such as heavily doped epitaxial layers and Base-Emitter junction epitaxial layers, exhibit lower voltage drops and impedance proportions. For size scaling predictions, transconductance (gm) is mainly affected by the Emitter mesa width and the path length between Base-Emitter electrodes, while capacitance (C) is positively correlated with pn junction width, as width is proportional to junction area. After scaling, the optimal fT values for type I and type II DHBTs are approximately 140 GHz and 450 GHz, respectively. To further optimize type I DHBT, we successfully increased fT to about 300 GHz by reducing the thickness of both the depletion layer and the base layer. Finally, we explored the differences in device characteristics between type I and type II DHBTs when the base layer thickness is reduced. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-27T16:43:39Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-27T16:43:39Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements iii
摘要 v Abstract vii Contents ix List of Figures xiii List of Tables xix Chapter 1 Introduction 1 1.1 Background 1 1.2 Two types of InP HBTs 3 1.2.1 Type I InP-HBT 3 1.2.2 Type II InP-HBT 4 1.3 Thesis overview 5 Chapter 2 Methodology 7 2.1 2D Poisson and Drift-Diffusion Equation for DHBT Device 7 2.2 Carrier Transport Properties and Simulation Model 9 2.2.1 Field-Velocity Relation Settings Schematic Figure 10 2.2.2 Tail State of Ec and Ev 11 2.3 Analysis of Cutoff Frequency 13 2.4 Whole Simulation Process Flow Chart 14 Chapter 3 Type I HBT simulation analysis 15 3.1 Epitaxial design analysis 16 3.1.1 Contact layer design 16 3.1.2 Junction layer design 18 3.2 Electron carriers transport properties of type-I DHBT 35 3.2.1 Saturation velocity of the field dependent 37 3.2.2 Minority carrier mobility (μn for base layer) 37 3.2.3 DOE on the type-I DHBT 38 3.2.4 Rc for base, emitter and collector 40 3.3 QAD chip fitting result of Type I DHBT 41 3.4 Scaledown prediction of the Type I DHBT 43 3.5 Type-I DHBT Optimization 47 3.5.1 BE junction design 47 3.5.2 BC junction design 49 3.5.3 Base layer thickness reduce 52 Chapter 4 Type II HBT simulation analysis 53 4.1 Epitaxial Design Analysis 53 4.1.1 Contact layer design 55 4.1.2 Junction layer design 56 4.2 Electron carrier transport properties analysis 70 4.2.1 Electron velocity properties of type-II DHBT 70 4.2.2 DOE properties of Type-II DHBT 73 4.2.3 Rc for base, emitter and collector 75 4.3 QAD chip fitting result of Type II DHBT 78 4.4 Scale-down prediction of the Type II DHBT 79 4.5 Analysis of type-I and II DHBT structures 84 Chapter 5 Conclusion 87 References 89 | - |
| dc.language.iso | en | - |
| dc.subject | 高頻元件 | zh_TW |
| dc.subject | 砷化銦鎵 | zh_TW |
| dc.subject | 雙異質接面雙極性電晶體 | zh_TW |
| dc.subject | 砷化鎵銻 | zh_TW |
| dc.subject | 磷化銦 | zh_TW |
| dc.subject | High-frequency device | en |
| dc.subject | Double heterojunction bipolar transistor | en |
| dc.subject | InP | en |
| dc.subject | InGaAs | en |
| dc.subject | GaAsSb | en |
| dc.title | 高頻磷化銦雙異質接面雙極性電晶體模擬分析與優化 | zh_TW |
| dc.title | Simulation analysis and optimization of high frequency InP double heterojunction bipolar transistors | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃建璋;吳肇欣;張子璿 | zh_TW |
| dc.contributor.oralexamcommittee | Jian-Jang Huang;Chao-Hsin Wu;Tzu-Hsuan Chang | en |
| dc.subject.keyword | 雙異質接面雙極性電晶體,磷化銦,砷化銦鎵,砷化鎵銻,高頻元件, | zh_TW |
| dc.subject.keyword | Double heterojunction bipolar transistor,InP,InGaAs,GaAsSb,High-frequency device, | en |
| dc.relation.page | 90 | - |
| dc.identifier.doi | 10.6342/NTU202500726 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-02-17 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | 2030-02-16 | - |
| 顯示於系所單位: | 光電工程學研究所 | |
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