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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳奕君 | zh_TW |
| dc.contributor.advisor | I-Chun Cheng | en |
| dc.contributor.author | 卜冠州 | zh_TW |
| dc.contributor.author | Kuan-Chou Buu | en |
| dc.date.accessioned | 2025-02-25T16:22:42Z | - |
| dc.date.available | 2025-02-26 | - |
| dc.date.copyright | 2025-02-25 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-02-12 | - |
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Zhou,, "Performance Improvement of Hf0.5Zr0.5O2-Based Ferroelectric-Field-Effect Transistors With ZrO2 Seed Layers," IEEE Electron Device Letters, vol. 40, no. 5, pp. 714-717, 2019, doi: 10.1109/led.2019.2903641. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96990 | - |
| dc.description.abstract | 本研究致力於研發以金屬氧化物半導體（Metal Oxide Semiconductor）搭配氧化鉿鋯（HfZrO2, HZO）鐵電材料製備鐵電薄膜式電晶體記憶體（Ferroelectric Thin Film Transistor, FeTFT），以應對新世代記憶體對高穩定性與低能耗的需求。嘗試從既有的金屬-鐵電層-金屬-絕緣層-半導體層（MFMIS）串聯架構[1]，精簡化為直接應用HZO鐵電薄膜作為FeTFT絕緣層之金屬-鐵電絕緣層-半導體層（MFS）架構，此縮減設計不僅降低製程步驟，還將同時避免介電材料堆疊引起的分壓問題。
本文先是系統性探討了HZO和金屬氧化物半導體各自的材料特性，並分析彼此搭配後電性間的交互影響。與此同時，針對過往FeTFT文獻發現以氧化銦鎵鋅（IGZO）作為主動層時，無法進行擦除操作的瓶頸[2]。實驗則以異質主動層設計，透過在HZO和IGZO中間額外引入富含氧空缺（Oxygen Vacancy）的銦錫氧化物（InSnOx, ITO）或氧化銦（In2O3）薄膜，成功解決HZO和主動層介面處正電荷不足無法形成電場極化之問題[3]。且基於前述成果，研究進一步以富含氧空缺的In2O3取代材料內部缺乏電洞的IGZO作為主動層，在低於350°C的環境下製備出具有穩定遲滯特性的FeTFT。除此之外，由於元件製備上須考量濺鍍之In2O3已具有極佳的導電性，不宜再進行高溫退火。因此後續加入金屬Mo作為犧牲層（Sacrificial Layer），以分段退火方式成功整合HZO和In2O3間的退火矛盾。 最終實驗結果顯示，雖然目前研發製備之FeTFT仍存在電流開關比不足與次臨界擺幅（S.S.）相對偏高等挑戰尚待後續改善與提升。然而，此精簡化MFS架構In2O3 FeTFT亦同步於脈衝方波測試中，成功驗證其極化狀態在無供電條件下依然能長時間保持，此記憶體操作成果揭示了本項研究所研發之FeTFT在多層式儲存應用和後段製程適配性上的潛在價值與可行性。 | zh_TW |
| dc.description.abstract | This research focuses on developing ferroelectric thin-film transistors (FeTFT) by integrating hafnium-zirconium oxide (HfZrO₂, HZO) with metal oxide semiconductors channels. The goal is to meet the demands of next-generation memory devices for high stability and low energy consumption. In this work, a simplified FeTFT structure is proposed, replacing the conventional metal-ferroelectric-metal-insulator-semiconductor (MFMIS) design with a more efficient metal-ferroelectric-semiconductor(MFS) structure[1]. In this configuration, HZO ferroelectric layer serves as the FeTFT insulator simultaneously. This new design not only significantly reduces fabrication process steps but also avoids voltage division issues caused by dielectric layer stacking.
However, FeTFT with oxide semiconductor channels often suffer from restricted memory window. This limitation arises from the inherent inability of n-type oxide semiconductors to generate an adequate number of hole carriers required for effective ferroelectric polarization switching[3]. To overcome this challenge, a heterostructure active layer is introduced, by inserting an oxygen vacancy-rich thin film at the interface between HZO and IGZO, such as ITO or In2O3. This approach resolves the low hole concentration problem, enabling reliable polarization switching in the HZO layer. Building on this, oxygen vacancy-rich In2O3 was further served as the active layer. Leading to the successful fabrication of FeTFT with stable hysteresis characteristics under low process temperature. Furthermore, to resolve the thermal mismatch between HZO and In2O3, a sacrificial Mo layer was introduced. The device was first annealed in an MFM structure to activate the ferroelectric properties of the HZO layer, and the sacrificial layer was subsequently removed. Although the experimental results show that our FeTFT devices still face challenges like low current on/off ratio and high subthreshold swing (S.S.), requiring further optimization. But nevertheless, our MFS structure In₂O₃ FeTFT successfully demonstrated its ability to retain polarization states for an extended period under pulse measurement, even without power supply. These findings highlight the potential value and feasibility of our FeTFT for multi-level storage applications and compatibility with back-end-of-line (BEOL) processes. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-02-25T16:22:42Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-02-25T16:22:42Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 I
中文摘要 II Abstract III 目次 V 圖次 IX 表次 XIV 1 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機與目的 4 1.3 論文架構 5 2 第二章 理論與文獻探討 7 2.1 薄膜電晶體簡介 7 2.1.1 薄膜電晶體之基本原理 7 2.1.2 薄膜電晶體之閘極偏壓能帶圖 9 2.1.3 薄膜電晶體之結構比較 10 2.1.4 薄膜電晶體之絕緣層介電材料 11 2.1.5 薄膜電晶之主要參數 12 2.2 氧化鉿鋯鐵電電容 16 2.2.1 鐵電材料 16 2.2.2 氧化鉿基鐵電性成因 17 2.2.3 氧化鉿鋯薄膜結晶相 18 2.2.4 氧化鉿摻雜不同比例鋯元素之鐵電電容 19 2.2.5 氧化鉿鋯鐵電性成因探討 21 2.2.6 電極材料對氧化鉿鋯鐵電性之影響 24 2.3 氧化鉿鋯鐵電記憶體 26 2.3.1 氧化鉿鋯鐵電記憶體之基本原理 26 2.3.2 矽半導體搭配氧化鉿鋯鐵電電晶體式記憶體 29 2.4 氧化銦鎵鋅與氧化銦之主動層 30 2.4.1 金屬氧化物半導體帶電載子傳輸簡介 30 2.4.2 氧化銦鎵鋅與氧化銦 31 2.5 金屬氧化物半導體搭配氧化鉿鋯之鐵電薄膜電晶體式記憶體文獻回顧 33 2.5.1 鐵電薄膜電晶體MFS架構對氧化鉿鋯鐵電性極化之影響 34 2.5.2 鐵電薄膜電晶體加入上閘極結構設計之探討 39 2.5.3 短通道鐵電薄膜電晶體之探討 41 2.5.4 結合不同金屬氧化物作主動層之鐵電薄膜電晶體探討 43 2.5.5 金屬氧化物搭配氧化鉿鋯鐵電薄膜電晶體之文獻回顧整理 47 3 第三章 實驗方法與步驟 48 3.1 薄膜沉積製程 48 3.1.1 原子薄膜沉積製程 48 3.1.2 射頻磁控濺鍍製程 50 3.1.3 電子束蒸鍍製程 52 3.2 光學微影製程 53 3.2.1 光阻塗佈 53 3.2.2 光罩對準與曝光 54 3.2.3 圖形顯影 54 3.3 蝕刻製程 55 3.3.1 濕式蝕刻製程 55 3.3.2 反應離子蝕刻製程 56 3.4 HZO鐵電電容MFM製備流程 57 3.5 MFMIS串聯架構FeTFT製備流程 60 3.6 MFS架構FeTFT與異質主動層製備流程 64 3.6.1 HZO鐵電電容之MFSM結構製備流程 69 3.7 以In2O3作為主動層之MFS架構FeTFT製備流程 70 3.7.1 HZO鐵電電容之MFM結構製備流程 74 4 第四章 結果與討論 75 4.1 HZO鐵電電容分析 75 4.1.1 MFMIS串聯架構FeTFT HZO C-V 電性分析（MFM結構） 76 4.1.2 MFS架構FeTFT HZO C-V電性分析（MFSM結構） 78 4.1.3 MFS架構異質主動層FeTFT HZO C-V電性分析（MFSM結構） 80 4.1.4 以In2O3作為主動層MFS架構FeTFT HZO C-V與P-V電性分析（MFM結構） 83 4.2 串聯架構MFMIS FeTFT電性分析 85 4.2.1 IGZO TFT電性分析 85 4.2.2 無交疊MFMIS串聯架構FeTFT電性分析 87 4.3 MFS架構FeTFT電性分析（以IGZO作為主動層） 89 4.3.1 退火方式對MFS架構FeTFT之影響 89 4.3.2 下閘極金屬前置處理對MFS架構FeTFT之影響 93 4.3.3 厚度對MFS架構FeTFT之影響 96 4.4 異質主動層MFS架構FeTFT電性分析 98 4.4.1 ITO-IGZO異質主動層MFS架構FeTFT電性分析 98 4.4.2 濺鍍氧通量對ITO-IGZO異質主動層FeTFT電性分析 103 4.4.3 In2O3-IGZO異質主動層MFS架構FeTFT電性分析 106 4.5 以In2O3作為主動層之MFS架構FeTFT電性分析 109 4.5.1 濺鍍氧通量對以In2O3作為主動層之MFS架構FeTFT電性分析 112 4.5.2 以In2O3作為主動層之MFS架構FeTFT脈衝寬度效應分析 115 4.5.3 以In2O3作為主動層之MFS架構FeTFT記憶體Retention分析 118 5 第五章 結論與未來展望 121 5.1 結論 121 5.2 未來展望 123 A. 附錄 124 A.1 MFS架構FeTFT HZO P-V電性分析（MFSM結構） 124 A.2 Al2O3介面層對MFS架構FeTFT影響 126 A.3 In2O3-IGZO異質主動層對MFS架構FeTFT影響 129 參考引用文獻 130 | - |
| dc.language.iso | zh_TW | - |
| dc.title | 以金屬氧化物半導體作為主動層之低溫氧化鉿鋯鐵電電晶體記憶特性研究 | zh_TW |
| dc.title | Memory Characteristics of Low-Temperature HfZrO2 Ferroelectric Thin-Film Transistors Based on Metal Oxide Channels | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李敏鴻;陳建彰 | zh_TW |
| dc.contributor.oralexamcommittee | Min-Hung Lee;Jian-Zhang Chen | en |
| dc.subject.keyword | 鐵電記憶體,FeTFT,氧化鉿鋯,金屬氧化物半導體,MFS,結構縮減, | zh_TW |
| dc.subject.keyword | Ferroelectric Memory,FeTFT,HZO,Metal Oxide Semiconductor,MFS,BEOL, | en |
| dc.relation.page | 138 | - |
| dc.identifier.doi | 10.6342/NTU202500676 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-02-13 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 光電工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 光電工程學研究所 | |
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